# Ultrasound transducer excitation - frequency, transistor type

I currently work on my ultrasound project. I need to excite my Olympus V305-SU-F tranducer with -100 V spike pulses. Unfortunately Olympus does not provide any kind of datasheet. I know only value of impedance - 50 ohms for resonance frequency (2,25 MHz). My circuit will be powered by DC/DC converter MAX5025.

I want to use following circuit for excitation:

At first the C1 is beeing charged to Vcc value through R2,R1 and T1 is closed. T1 will conduct after short positive impuls to its base and C1 is discharged into transducer X.

BUT, how can I determine the pulse frequency? Is it given by C1 capacity? So if I want 2,25 MHz pulse I need pulse with duration about 0,44 ns?

In the description of the circuit above, its said, that I need avalanche transistor. Why? I still don´t understand how will the transistor type affect the speed of discharging of C1.

• Try adding component values to the schematic. Also add a link to the "description" you mention. Commented Jan 21, 2016 at 17:49
• Why do you want to use this circuit? 2.25MHz has a period of 440ns, half cycle 220ns. For 100V 50ohms this type of circuit would waste a lot of power. I would use a MOSFET driver, either push-pull configuration or a resonant circuit. Commented Jan 21, 2016 at 17:55
• Andy aka: I have not calculated values yet. For first step I want to know, if it is good to use this kind of circuit or not. Unfortunately, the description is not in english, but in czech. It is from book. Commented Jan 22, 2016 at 17:32
• user1582568: Because I don´t know about better solution for now. Do you know why the avalanche transistor is needed? Commented Jan 22, 2016 at 17:35

I want to start by clearing up a couple of errors. 1) The time period for a 2.25 mHz is 0.444 us or 444 ns. 2) The operating frequency is determined by the frequency of the input signal, not by C1, R1, R3, etc..

It is correct that when T1 is off (not conducting), C1 "attempts" to charge (through R2 and Rdis) to Vcc. However, when T1 in on (full conduction), C1 discharges through transducer X in series with R3, with R1 in parallel but high enough to be ignored.
Since the charging and discharging are determined by the respective RC time constants, if the time between input pulses is "too short," C1 will not charge to the maximum value because it will be discharged as soon as T1 is turned on.
Typically, you have to allow 5 RC time constants to fully charge and discharge a capacitor. So, to allow the capacitor to fully charge, ((R2 + Rdis) X C1) X 5 > 247 ns, and to fully discharge ((50 + R3) X C1) X 5 < 197 ns.
I arbitrarily assigned more time to charging (247 ns) and the remaining (197 ns) to discharging. So, the input signal should be on for 197 ns, and off for 247 ns. You will have to "play" with the values of C1, R1, R2, and R3, to meet the required rise and fall times.
With regard to the "avalanche" transistor, all I can think of is that they have "sharper" response times, therefore, the output signal would have"sharper" edges.

EDIT: After resting a while, I went back to your circuit and made a "first pass" at determining the related component values and they are:

R3 = 10 ohms; R1 = 6k ohms; R2 = 15 ohms; and C1 = 658.8 pf

• Thank you! You helped me alot. I did not know about MOSFET solution in second answer. I will probably use MOSFETs. I found good book which covers this topic (online pdf link): ia801507.us.archive.org/18/items/… Commented Feb 16, 2016 at 18:37

A pretty standard circuit would be to use a P-Ch and N-Ch MOSFET in a half bridge configuration. Something like this:

Image Source

You can buy (as shown in that circuit) ICs which consist of complementary high voltage MOSFETs, and also integrated MOSFET drivers.

Alternatively you can built that circuit pretty much as shown from discrete components.

Essentially the circuit first level shifts using a MOSFET driver from a logic level signal to somewhere in the region of 10V drive signals for the MOSFET gates. These are then capacitively coupled to the MOSFET gates. This coupling allows the gate to be re-biased to the power supply rails of the MOSFETs (e.g. +/-100V) and also provides some isolation between the low and high voltage.

The MOSFET gates have resistors from gate to source as well as a zener diode. This pair is what (a) provides the bias to the control signals, and (b) protects the gate from over-voltage.

There are many similar devices to the ones shown, including integrated pulsers which have the whole chain built in. This topology is quite standard, though you frequently see more than one half bridge connected together to form a 3-level or even 5-level pulser.

If you only need a Unipolar pulse, the negative supply rail can be omitted, connecting the NMOS source to ground instead of a negative voltage. This would give you a positive unipolar pulse. If you need a negative pulse you can either bias the other side of the XDR to +100V, or you could connect -100V to the NMOS and 0V to the PMOS.

• Good explanation. I would add (explanatory only) that using a proper gate driver (such as you have shown) permits fast turn-off times as well as fast turn-on, minimising the dead time required to prevent shoot-through. Commented Jan 31, 2016 at 14:29
• Thank you! I´m going to use MOSFET - unipolar pulses. I found book which covers this topic (online pdf link): ia801507.us.archive.org/18/items/… Commented Feb 16, 2016 at 18:39
• In data sheet they mention 200 V breakdown voltage. Can I apply higher powering voltage than 100 V, but below 200 V? I´m not sure about this from datasheet. Commented Feb 18, 2016 at 11:49
• Maybe this one -> microchip.com/wwwproducts/en/TC1550 Commented Feb 18, 2016 at 12:14
• I think I have found my answers in this app note: ww1.microchip.com/downloads/en/AppNotes/AN-H53.pdf It shows how to generate -200 V unipolar pulses with TC6320 Commented Feb 18, 2016 at 14:07