I have just used an IP in the IP catalog called Multiply accumulate. This IP is supposed to multiply 2 inputs and accumulate the result. I made a control module for it(mac_control) where I instantiate this IP (mac: entity work.MAC port map...) and then I made my test bench. Everything compiled as it should but when I go to the simulation, it doesn't output anything.

I noticed that the port map pins that I set forcefully (for example, ce => '1', rst => '1', etc) were not displayed in the simulation. I don't mean that they they were marked as undefined, I am saying that there was just the black background where the signal should be. So I created internal signals which were initiated with the expected values (signal int_ce : std_logic := '1') and then I linked the signal to the port maps. This made the signals appear on the vivado simulator, but still ... no output.

Maybe I'm missing a library or something. Does anyonw know how to simulate the IP core?

EDIT: I also tried using the '*' and '+' operators but vivado told me that 0 definitions were found for those operators. I'm almost certain that this means that a library is missing. But I can't same the same for the main problem

EDIT2: I noticed something else. When I open the sources it lloks something like this:

tb -> multiplier.vhd -> mac.xci -> mac.vhd (this one has a red flag) -> xbip_multaccum_v2_0


I guess there may be something wroong with the mac.vhd. A red flag doesn't strike me as a good thing (it's a little red square at the bottom levt part of the icon in Vivado)