I would like to model a clock signal with an drift parameter in my digital simulation.
The current implementation handles:
- frequency / period
- phase -360.0 .. 360.0 degree
- duty cycle 0.0 .. 1.0
For clock domain crossing circuits, I would like to implement a primary (stable) and secondary (drifting) clock. I know that my digital model can not handle metastabiliy problems -- that not my goal at all -- but I could detect handshake errors.
*Clock drift is not jitter. Clocks running at the same speed may varie in sub percent ranges, so one circuit is running a bit faster.*
Most documents have only ratings for jitter, on the other hand transceivers, like in FPGAs, have phase compensation units which do phase correction automatically. I can't find a max value for them ...
So my questions are: - Is it an absolut or relative value? - If relative, relative to what: one cycle, 1 second, ...?
If someone has suggestion on how to model jitter, it will be welcome too :).