# Displaying signals in testbench from counter VHDL

Say I have a count signal in a counter VHDL file and want to display this in my simulation output, what would I have to do to my testbench to output such data?

• To display it in the wave window, or to access it at the top level (in the testbench code)? Jan 24, 2016 at 15:13
• @BrianDrummond displaying it in the wave window, I have tried just doing signal count: std_logic; but as expected it came up as an undefined value. Jan 24, 2016 at 15:15