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I'm curious how one particular company Gigabyte ensures its server motherboards to run at the maximum supported memory frequency even when there're two or three DIMMs per channel (of coure we're talking about RDIMMs and not UDIMMs). What trick they use in such motherboard to achieve that: (look at the overview section)

Some time ago I read a leaflet claiming that on Haswell-E/EP motherboards populating them with more than one module per channel decreases the frequency:

  • 1 DPC = max 2133 MHz
  • 2 DPC = max 1866 MHz
  • 3 DPC = max 1600 MHz

Some other motherboard manufacturers put a condition on their specifications, something like 2133MT/s@1DPC only, whereas Gigabyte boasts that its products reach 2133MHz frequency even with 3 DPC.

How such feature meant to be done?

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  • \$\begingroup\$ You mean other tricks than marketing lies? \$\endgroup\$ – PlasmaHH Jan 24 '16 at 22:07
  • \$\begingroup\$ I'm totally serious. I have no idea how it could be done, but I only suppose they can use some trick like assert frequency while prolonging each command to two cycles (that is only my guess). With UDIMMs there's something similar. Currently I have Asus X99 Deluxe with 64 GB of UDIMM DDR4 memory in configuration: 8 x 8GB modules and in BIOS and under linux using dmidecode I see the full speed 2133 even I have 2 DPC. In this case the 2133 freq. is assured by sacraficing latency and introducing so called 2T or 2N timming for UDIMMs. Maybe that's something similar? \$\endgroup\$ – Adam Przedniczek Jan 24 '16 at 22:17
  • \$\begingroup\$ Or maybe they detects such situation (2 & 3 DPC) and overclock both modules and memory controller by increasing the voltage supplied to CPU on some one pin? \$\endgroup\$ – Adam Przedniczek Jan 24 '16 at 22:55
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I cannot speak for specifics of DIMMs in your case, but I can speak for designing other boards with high speed memory. I would expect that you would need to either 1) increase the voltage, 2) increase the gain on the inputs by increasing the current, or 3) decrease the amount of memory to keep the same speed.

When I make ICs, my IO drivers are fixed for current; however, some memory modules IC I can configure with pins to have lower effective input capacitance but burning more power on the input.

In the case of #1, assume that you have a fixed driver strength on the IC, if you add more ICs on the bus, you increase capacitance so you need to slow down the bus to hit timing.

In the case of #2, you burn a lot more current by making the inputs look like they have less capacitance.

In the case of #3, you will find that there's a refresh penalty on DRAM. If you have a 2x size of DRAM IC, you need more time to refresh. Usually, this looks like just slower bus activity in a speed test, but sometimes you actually decrease the speed of the IO and still have a fast "refresh" clock.

I have personally added more DRAM ICs and then had to burn more current to hit timing due to the addition of another IC on the bus.

I think that what you have in the end is just marketing, and that all of the bus transfers must slow down as you add DIMMs. Micron DDR4 document suggests such as well.

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