To amplify Mr. Lathrop's answer: timing diagrams have two aspects: (1) what a device will do, and (2) what a device will expect from other devices. Timing diagrams almost always combine some of both (since most devices exist for the purpose of causing some response to external signals). In many cases, some signals on the timing diagram will show what's assumed on the input, and others will show what's assumed on the output; sometimes bidirectional signals may combine both. My preference for timing diagrams involving bidirectional signals is usually to have input and output functions shown on different lines; when they're on one line, it's sometimes easy to tell what's input and what's output, but sometimes it can be confusing.
With regard to device inputs, there are a few "symbols" to be aware of. A line which is solidly high means the input is assumed to be high. Likewise one which is solidly low. A line which sits in the middle or one which is cross-hatched high and low means that the device won't care what the input does at that point; it could sit high, sit low, or bounce arbitrarily between high and low. If the line starts high and then goes low with a bunch of parallel diagonal lines, that means the device will expect the input to go from high to low exactly once, but won't care precisely when it happens. Likewise if the line starts low and goes high. If there are parallel horizontal lines at high and low, that means that the signal may legitimately be high, or it may legitimately be low, but must remain in its present state for the duration of the indicated part of the diagram.
With regard to device outputs, the "symbols" are mostly similar, except that they either indicate what the device can be expected to do or indicate when the device can't be expected to do anything in particular. The one major difference is that a line centered between high and low does not mean unspecified behavior--it means that the device is guaranteed not to output a strong high or a strong low (the device may output very weakly high or low, but not so strongly that any other device would have difficulty whatsoever overpowering it).
An important thing to note with timing diagrams, by the way, is that they are generally not drawn to any particular horizontal scale. Certain moments in time will be labeled, with labeled arrows connecting them. Generally, the function of a timing diagram is to make statements like the following:
- For correct operation, event X must happen at least time t before event Y
- For correct operation, event X must happen within time t of event Y
- For correct operation, event X must happen between time t1 and t2 of event Y
- For correct operation, event X must NOT happen between time t1 and t2 of event Y
- If event X happens, device will output event Y within time t
- If event X happens, device will output event Y no sooner than time t
- If event X happens, device will output event Y between time t1 and t2 afterward.
An important thing to realize is that the statements made by a timing diagram are often independent. If signals are not marked as having any particular timing relationship relative to each other, their relative placement on the diagram should be regarded as coincidental. For example, the timing diagram for a ROM chip might show /CS going low, and then /OE going low, and have an arrow from the falling edge of /CS to the output with a labeled time of 100ns, and an arrow from the falling edge of /OE to the output with a labeled time of 50ns. Such a diagram does not mean the falling edge of /OE must occur before the edge of /CS. It means that the state of the output is not guaranteed except when /CS has been low for at least 100ns and /OE has been low for at least 50ns. Unless explicit timing relationships are stated between /CS and /OE, they may go up and down arbitrarily, with the sole caveat being that unless they have been low for the required durations there's no guarantee as to what the chip will output.