# Some question about RTL Design and VHDL

I have some question almost uncorrelated, so I'll enureamted it, hope you can help me:

1) I'm studing RTL Design, and the question is at level of data path, arithmetic unit ecc. I don't understand why and how a shifter can be used to do the multiplication and division operation. For example, if someone ask me "how many adder (or shifter) is needed to do a multiplication between to operand composed by X bit", what is the method that I have to apply to answer this question? Another question. In a book I've read that the operation A+B=K, in wich the output is 1 if the sum of A and B is egual to K, 0 otherwise, can be performed evaluting the Carry expected and Carry obtained by summation. I didn't understand this concept, can you please explain me?

2) VHDL. This question is simple, I think. In all example in the books, when a flip-flop is present, the rising edge of the clock is managed in this way: process(clk), and then for expalin the rising edge there is a line "if(clk'event & clk = 1)". The question si: why "clk'event" is necessary? The signal clk is inside the process, so we go inside the process each time the clock change its state, isn't sufficient to evalute only if clock is egual to 1, because the clk'event is Always true?

Thank you

• This should help for your first question: en.wikipedia.org/wiki/Arithmetic_shift – deinoppa Jan 26 '16 at 8:31
• There are many different multiplier architectures, the basic concept is also explained on wikipedia: en.wikipedia.org/wiki/Binary_multiplier – deinoppa Jan 26 '16 at 8:38
• For part 2: Sensitivity lists are ignored by synthesis tools, so if your HDL code should also be useful for synthesis, then you should apply this pattern or use if rising_edge(clk) then. Another reason is flexability. You don't need to rewrite your code if you extend the register description with an asynchronous reset. – Paebbels Jan 26 '16 at 10:55

For part (2) - if the sensitivity list of a process contains other signals, and there is activity on those signals while clk = '1' then the process will operate multiple times per clock cycle. If it's a counter, that would be bad...
Incidentally, if(clk'event & clk = 1) has been obsolete for over 20 years; so your teaching materials are sorely out of date. As @Paebbels says, use if rising_edge(clk) instead.