I'm trying to optimize a verilog code and I found something that I don't feel it's correct. I found a module that has an output and it's using that output value as a condition in a case statement. There is an example:
module TT
(
output reg Busy = 1'b0
, output reg Finished = 1'b0
, input wire clk
, input wire rst
, input wire start
, input wire [ 5 - 1 : 0 ] freq
);
always @ (posedge clk)
begin
if(!rst)
begin
case(Busy)
1'b0:
begin
//do some logic...
if(something)
Busy = 1'b1;
end
1'b1:
begin
//do some logic...
if(something_else)
Busy = 1'b0;
end
endcase
end
end
endmodule
Is it good practice to do this? If not, why? Thanks a lot.
else
can cause latch. Use of non blocking statements is required. \$\endgroup\$ – sharvil111 Jan 29 '16 at 12:32