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I am trying to understand the parameters in an ADC datasheet. The precise parameter being the INL(integral non linearity). Now, I was going through this website INL website.

ADC error. Now, there is another website that shows the ADC error of a 12 bit ADC as 0.00024. The other website.

ADC quantisation error..

In the former it is in terms of percentage so I understand. But why a factor of 0.5 or 1/2 is present ?

The ADC I am using is the ADS62P15. In page 5 of the datasheet I see the INL defined (typical) as +/-1 (LSB). Now, is this a percentage value ?

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2 Answers 2

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You are mixing things up. There are multiple errors in AD conversion. Differential nonlinearity error, gain error, offset error, etc. For this example i'm making up a 2 bit ADC, max Vin 4V.

  1. Quantitization error: Always +/- 1/2LSB. This makes your translation function in shape of steps. Our ADC has 4 codes, 00, 01, 02, 03. If the voltage is between 0 and 0.5V it will always return a 00, for voltage between 0.5 and 1.5 it will always return 01. LSB in our case is 1V (25%).

Quantitization error

2.Integral nonlinearity error makes the ideal straight line transfer function bend. This means that some bits are larger voltage "steps" then other. One bit covers more voltage if it is lower, than if it is higher. So in INL tells you "how much does the Quantitization error" increase over the whole range of input voltage. Your datasheet says +/- 1 LSB for INL. If we say the conversion at 1/2 of the voltage range is with out error, This means you get an extra error of 1LSB at 0V and at maxV. If you don't compensate that it may induce an error of one 1 LSB. So you can't rely on the last bit. If your error is +/-1LSB in 11bit system this means 1/(2^11) or 0.048%.

Your error all together (only quant. error and INL) is 0.054%. Read more about the errors here.

INL error

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  • \$\begingroup\$ Thank you for the explanation. Now, when you say the quantisation error is 0.5LSB, is it universal ? Will ADCs always have this value. Then if the INL is a measure of the deviation or skew of the quantisation error, will this not be added up to get a kind of total or sum error ? \$\endgroup\$
    – Board-Man
    Commented Jan 29, 2016 at 14:14
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    \$\begingroup\$ please read again why quantitisation error occurs... You are basically cutting the voltage range in parts. LSB is the smallest part you can detect, so if you speak in LSB all ADCs have the same quantitization error in unit of LSBs, but as ADCs with more bits have more codes, they have have smaller "parts of voltage", which means one LSB is less in unit of Voltage for 2 bit and 24 bit adc. This means quantitization error is less for the ADC with more bits. \$\endgroup\$
    – ursusd8
    Commented Jan 29, 2016 at 16:24
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    \$\begingroup\$ If i return to my example, 2 bits mean 4 codes. at 4V you will get code 01 for all votages from 0.5 to 1.5V. As LSB is 1V (range/all codes, or how much does adding one bit(LSB) add to voltage) the error is +/-0.5V or +/-0.5LSB. If you use different ADC, let's say 3 bit, you have 8 codes. one LSB is now 0.5V. You will get 000 for voltages 0-0.25; and 001 for voltages from 0.25 to 0.75m which is again +/-0.5LSB, but is only +/-0.25V \$\endgroup\$
    – ursusd8
    Commented Jan 29, 2016 at 16:26
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    \$\begingroup\$ As for the adding errors, you add the errors in the same way as most of the errors in nature are added with Euclidean Distance. Please read the link at the end of my original answer. \$\endgroup\$
    – ursusd8
    Commented Jan 29, 2016 at 16:29
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No, a +/- 1 LSB error is not a percentage value except in the special case of an unusual ADC with a total range of 100 steps.

Most (virtually all) ADCs have binary outputs so an n-bit ADC can encode the input as 2n steps, so an LSB is 1/(2n) or 2-n of the full scale output.

So a 1 LSB error is 1/2N of the full scale output or (100 / 2N percent) of the full scale output.

EDIT : you are thinking along the right lines. If your 8-bit ADC has a +/-1LSB INL error that means your readings will be within +/-19mv of the actual value.

Your first table makes another point : even in a perfect ADC there is still an error due to quantization : the process of rounding a real value to the nearest integer equivalent. This introduces an error of up to 0.5 LSB hence the additional 1/2 in your table.

Your third comment is simple to understand : 4 LSB-sized steps of a 12-bit ADC are the same as 1 LSB of a 10-bit ADC.
Or put another way, 4 * 1/(2^12) = 1 * 1/(2^10)

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    \$\begingroup\$ Thank you for the explanation sir. Now, the LSB stands for least significant bit.Now, suppose I have an 8 bit ADC of 1LSB INL rating. So, assuming that the Vref of the adc is 5V, then the error (1LSB) is translated as (1/256)*5 = approx 19mV. So, what the 1LSB means is, if I use this adc on a 5V Vref , my readings can be +/-19mV offcourse from the ideal response, right ? \$\endgroup\$
    – Board-Man
    Commented Jan 29, 2016 at 13:46
  • \$\begingroup\$ Also, in the 1st image of my question why is there a 1/2 in the ADCerror calculation please ? What does that signify ? \$\endgroup\$
    – Board-Man
    Commented Jan 29, 2016 at 13:49
  • \$\begingroup\$ I also happened to read an article from MAXM Semi - Linke - maximintegrated.com/en/app-notes/index.mvp/id/748 "For example, a 12-bit ADC with 4LSBs of integral nonlinearity error can give only 10 bits of accuracy at best (assuming the offset and gain errors have been calibrated)" How can a 4LSB give an accuracy of only 10bits ? What seems the logic behind that ? \$\endgroup\$
    – Board-Man
    Commented Jan 29, 2016 at 13:53
  • \$\begingroup\$ 4LSB of INL error renders the last two bits unreliable, so the 12-bit resolution in that (extreme) case is the same as a good 10-bit ADC with two unreliable sub-LSB bits. \$\endgroup\$
    – MarkU
    Commented Jan 29, 2016 at 22:05

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