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I have the above assignment and here's what I have so far in verilog:

module eightbit_palu(input [7:0]a,
                     input [7:0]b,
                     input [1:0]sel,
                     output [7:0]f,
                     output ovf);
     reg (f, ovf);
     always @ (a, b, sel);
     case(sel)
         2’b00: f = a + b;
         2’b01: f = ~b;
         2’b10: f = a & b;
         2’b11: f = a | b;
     endcase
endmodule

I'm new to verilog so I'm not sure if this is right or what I should do about the overflow value. Any tips/suggestions?

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closed as too broad by Daniel Grillo, PeterJ, Dmitry Grigoryev, Bimpelrekkie, uint128_t Apr 26 '16 at 2:36

Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

  • \$\begingroup\$ but those are declared in the module so are they still necessary? \$\endgroup\$ – smd Jan 31 '16 at 18:20
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    \$\begingroup\$ I'm not sure this is the best place to ask for homework help. If you have any questions about theory, or a project, we'd be more than happy to help, but answering your assignment questions for you seems a bit unethical. \$\endgroup\$ – Robherc KV5ROB Jan 31 '16 at 18:48
  • \$\begingroup\$ I asked for tips and suggestions (which is what I got), not an answer @RobhercKV5ROB \$\endgroup\$ – smd Jan 31 '16 at 18:50
  • \$\begingroup\$ Keep in mind that the concept of "overflow" means different things in different contexts. If you're just talking about unsigned numbers, then "overflow" is any number that doesn't fit into the same number of bits -- i.e., the carry output of the adder. However, if you're talking about signed numbers (2's complement), where the sign bit is the MSB of each number, then an "overflow" has occurred whenever the value of the sign bit does not match the value of the carry out bit. In other words, overflow = carry out XOR sign. \$\endgroup\$ – Dave Tweed Jan 31 '16 at 21:44
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Given that you have shown effort and done most of it, some hints:

  1. ANSI module declaration:

    The standard way of declaring modules is as follows:

    module <name> (input  <wire>        <width> <name>,
                   output <reg or wire> <width> <name>
                  );
    

    So for example:

    module test (input       [7:0] a, //Input 8 bits wide
                 input wire        b, //Input 1 bit wide - 'wire' is optional
                 output reg  [2:0] c, //Output register 3 bits wide
                 output reg        d, //Output register 1 bit wide
                 output wire [4:0] e, //Output wire 5 bits wide
                 output      [4:0] f  //Same as above - 'wire' is optional
                );
    

    The way you have done it, using the extra reg directive in the body of the module may work on some synthesizers, but it will definitely not work on all - some will complain about redeclaration of ANSI ports.


  1. Getting the overflow from an Addition

    There are several ways of getting the overflow from an addition. Firstly, create a module which does addition with overflow. Secondly, create a function which does the same thing. Thirdly, and probably most simple, use concatenation.

    For the third option, something like this is quite possible. This is an example for a 4 bit adder with carry out.

    wire       cout;
    wire [3:0] sum;
    wire [3:0] a;
    wire [3:0] b;
    
    assign {cout,sum} = {1'b0,a} + {1'b0,b};
    

    I will let you convert that into your code. But essentially what it does is make the inputs a and b 5 bits wide by concatenating 1 bit of 0 as the MSB. The output of the addition will then be 5 bits. The output of this addition is then fed into both cout and sum. Because the two are concatenated together, the sum gets the lower 4 bits of the addition, and the cout will get the upper bit.

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