I have just tested my second design with STM32F2, now it is STM32F207ZFT6, the ADC behaviour is the same as in my first application - strong noise in ADC.

Essential part of the board schematics

Noise of current input without any signal connected :

signal received with floating pin

Note : In the signal graphs above, the vertical axe is in ADC-bits, not in volts!; don’t be confused by its legend „[V]“, for this test we have used our modified program to see rough ADC data.

The same noise appears even when the CPU analog pin shortcircuited to GND, as shown here: input signal with pin shorted to ground

There are permanent spikes over 30 LSBs and more in the sampled signal, although they shouldn’t exceed 5-10 LSBs, by my opinion.

Another details :

  • 2-side PCB, on the bottom side there are other connections but most of it is poured with GND signal - common for both digital and analog, the analog ground is not separated. As the board consumption is minimal, below 100 mA, I think it should not cause such noise.

  • voltage reference VREF 3.3V buffered by opamp, blocked by 100nF and tantallum 10uF in parallel, the same with VREF/2; each of the processor power pin is blocked with 100nF cap

  • in our older application we used the same design concept, but the processor used was AduC834; it has 12-bit ADC too and the signal noise was several LSBs only, there were no problems; main difference was that the AduCs internal voltage reference was used, no external one

  • we have tested to disconnect processor analog ground pin from the board common GND and to connect it with extra wire directly to the voltage reference VREF ground, no effect

  • it is three-phase network measuring device, there are 3 analog voltage channels and three current channels with switchable gain preamplifier; the CPU oscillator 25 MHz, internal clock 120 MHz by PLL, ADC-clock is 30 MHz(in compliance with techspecs), we have tested to slow main internal clock (therefore all secondary clocks too) downto one quarter, but without any effect

  • ADC samples periodically input signal with rate 128 conversions per 50 Hz network period, i.e. each 156 usecs; results are transferred by DMA into internal RAM; data from the RAM are transferred via insulated RS485 (on another board) and visualized in our program. We have tried to prolong conversion times to maximum, no effect

  • excluding CPU, there are only 3 opams, 2 analog switches, I2C thermometer and three ULN-switches(unused during test), powered by linear LF33 stabilizer, normally powered by 5V DC from switcher on another board, but during the test the switcher was disconnected and the LF33 was powered from clear laboratory 5V DC supply. I am sure nothing but the processor oscillator can oscillate on the board.

  • checking the signal with oscilloscope doesn’t get decisive results, the signal is too weak

Anybody with this processor family ADC performance experience ?

Concerning the signal strength : even if the analog input is shortcircuited, I see noise of 5-10 mV (peak-to-peak) on oscilloscope - measured with coaxial cable with minimum ground wire length soldered to the board. With standard probe, the noise was about twice higher probably due to worse grounding (general EMC noise ?).

This is an image of my board: image of assembled board

And the bottom of the board: image of bottom of board

As I reported above, even if signal grounded, noise of about 30 LSBs still persists in the ADC converted data.

  • \$\begingroup\$ You say the signal is too weak, how weak is that? \$\endgroup\$
    – Kortuk
    Commented Oct 28, 2011 at 11:49
  • \$\begingroup\$ I have reported my problem in the ST forum too, there are all links (including board photo) there : my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/… \$\endgroup\$
    – Milan
    Commented Oct 31, 2011 at 13:00
  • 2
    \$\begingroup\$ I'm not seeing anywhere near enough bypass caps on that board to make me comfortable, and they're all pretty far form the part. \$\endgroup\$ Commented Nov 11, 2011 at 5:27
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    \$\begingroup\$ @Fake Name - Milan is not misusing the term, reference to "x LSB's" refers to x times the linear value of the least significant bit. However, "x bits of noise" could refer to 2^x LSBs. \$\endgroup\$ Commented Nov 17, 2011 at 16:44
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    \$\begingroup\$ @Chris Stratton - I disagree. "x bits of noise" is synonymous with "x LSBs". As such, saying "x times the LSB value" would mean x times the linear value of the least significant bit. However, x LSBs means the x least significant bits, or a linear range of 2^x. \$\endgroup\$ Commented Nov 17, 2011 at 21:12

4 Answers 4


I would argue that the ADC has a 4th input in addition to the three cited by Fred: its clock. At least for some types of ADCs, jitter or phase noise on the clock can impact ADC measurements.

You say you have a 25 MHz oscillator but are running the ADC at 30 MHz, so you have some PLL involved in the generation of its clock. If that is not working well, its irregularity could be a source of conversion noise. Can you try changing the software configuration (even temporarily) to not use the PLL and just run off of a the input clock or divided down from it?

I believe some microcontrollers also have a mechanism for suspending most of the digital circuitry while taking an ADC reading in order to reduce noise. You might look into seeing if something like that is possible.


There are many possible reasons for the noise you're seeing. It's important to understand that an ADC has THREE inputs:

  1. The input pin(s) (the one designed to be the signal input)
  2. The reference input(s) (Dout = 2^n * Vin/Vref)
  3. The power pins (supply + gnd)

Noise on any of those could create the noise you're seeing, and assuming the ADC itself is not defective, the noise must be getting in through one of those three paths.

It's possible to have decent ADC performance using the same ground for analog and digital, but you have to carefully lay out the PCB so that all the digital loop currents are isolated from the analog loops.

In this context, a loop is the entire current path a signal or power supply line (which should be considered a "noise" signal in this context) takes on the PCB. So for a power supply line it would be from where the power enters the board, along the trace until it gets to the power pin, through all the transistors in the IC, out the ground pin, then along the path of least resistance back to where the power enters the board. That's one power supply loop.

But if you do a good job with supply bypassing, there won't be much AC current in that loop, because you will have a much smaller, more localized loop of supply side of bypass cap to power pin to ground pin and back to ground side of bypass cap. If all your digital supplies are tightly bypassed, your power supply loop will be mostly clean and all the noisy digital constrained to short bypass cap loops.

The signal loops (including the Vref loop) work the same way - the signal comes in, winds its way to the ADC, out the ADC GND, and back to the signal ground (hopefully the same location where the signal started). If that loop crosses a digital loop, you can get noise injected. So typically a good mixed-signal design that uses one GND for analog and digital will keep the digital all on one side and the analog all on another, with GND at the end of the board right at the dividing point. It's usually not that cut-and-dry, you have to make compromises, but that's the idea.

Your mention "As the board consumption is minimal, below 100 mA, I think it should not cause such noise." It's more to do with how well the system is bypassed. A 100mA system with poor bypassing is going to have a lot more digital noise in the ground plane than a 1000mA system with good bypassing.

Hope this helps...


I have redesigned the PCB to 4 layers. And - what a surprise - the noise is off ! Further details here.

  • 1
    \$\begingroup\$ @ogurets And it's broken again. I hate link answers and vendor forums. "The page you were looking for was moved or doesn't exist." \$\endgroup\$
    – Navin
    Commented Apr 28, 2020 at 2:52
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    \$\begingroup\$ @Navin I so feel your pain... Googled by "STM32F2 ADC Signal Noise", post date October 28, 2011 (for the next time they move it): community.st.com/s/question/0D50X00009XkaFz/… \$\endgroup\$
    – ogurets
    Commented Apr 29, 2020 at 20:16

The board design really doesn’t respect recommended general rules.

We have retested it again.Typical noise of standard board is on Fig1 at https://i.sstatic.net/a7WY1.jpg .

To confirm the problem is caused by wrong grounding, we have done following modifications :

  • reinforced common grounding (modified board on Fig2 and appropriate noise on Fig 3)
  • separation of analog ground from the digital one and their mutual interconnection at the VSSA processor pin (Fig 4).

None of them helped. So I am rather afraid the problem can occur again even after redesign to 4-layer PCB …

To test PLL influence, we switched it off and the core was clocked by external 25 MHz crystal only. The noise dropped down (Fig 5), but I looks that it was caused by lower system clock only (normally, the core is clocked by the PLL’s 120 MHz), not by stopped PLL, because when we reswitched back to the PLL at 25 MHz, the noise was the same as that without the PLL running.

The only noticeable effect was reached by measuring the VREF/2 signal via individual processor pin simultaneously with each voltage and current pair using the third processor ADC and substracting it from voltage and current signals – then modulated noise is reduced to about one half (at https://i.sstatic.net/g6Q1M.jpg , upper red graph=standard signal, lower blue graph=signal after measured noise substraction). But I cannot use the third ADC for noise measurement, I need it for another task, so this is not a solution for me.

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    \$\begingroup\$ This is not an answer and so should not have been posted as such. That said, the PLL'd clock input to the ADC at 1:1 of input oscillator is probably a lot cleaner than at an oddball ratio thereof. If you suspect common mode noise, you need to look at things all the channels have in common... \$\endgroup\$ Commented Nov 17, 2011 at 16:37
  • \$\begingroup\$ Normally, external osc 25 MHz is internally divided to 1 MHz and this frequency is used to controll PLL; its 120 MHz system clock is divided by 4 to get 30 MHz ADC clock. During the test, the system clock was 25 MHz (both direct from ext osc and using PLL) and the ADC was driven from it directly(prescaller set to 1), i.e. it run at the same 25 MHz. Concerning your 2nd idea, you mean probably to switch core into sleep mode during ADC conversion; ADCs are served by DMA that cannot be simply switched off. But, although not usable at our application, I agree it would be interesting to try it. \$\endgroup\$
    – Milan
    Commented Nov 18, 2011 at 6:52
  • \$\begingroup\$ Precizing my previous comment : I forgot there is divider on the PLL output; so in fact, normally the PLL runs at 240 MHz and divided by two to get the system clock; during the test, the PLL run at 200 MHz and divided by eight to get 25 MHz system clock. \$\endgroup\$
    – Milan
    Commented Nov 18, 2011 at 7:17
  • \$\begingroup\$ @ChrisStratton it seems to be detailing how he resolved the issue, does that not seem like an answer? \$\endgroup\$
    – Kortuk
    Commented Jul 23, 2012 at 18:07
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    \$\begingroup\$ @Kortuk "None of them helped. So I am rather afraid the problem can occur again even after redesign to 4-layer PCB …" To me, it feels that this answer should be added as an edit to the original question. His second answer seems to describe how he resolved the issue. \$\endgroup\$
    – m.Alin
    Commented Jul 23, 2012 at 19:27

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