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I need to try different 74lsxxx logic ICs over a FPGA. As examples 4 bit adders, counters, etc which are more complex than primitive logic ICs. And it is time consuming and error prone to code in Verilog. Is there a easy way to directly import 74lsxxx IC gate schematics into FPGA synthesis tool?

P.S. I found Aldec's Active-HDL supports for net-list import. But I could not find a 74LS family net-list library.

And I found there was a very old software called viewlogic which had a 74LX library. Seems it is no loner available.

Thank you..

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2 Answers 2

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You need to re-think your approach to Verilog.

Being able to say c <= a + b; (adder) or i <= i + 1; (counter) on signals that can have arbitrary bit widths is much more concise and less error-prone than wiring up 4-bit chunks of 74xx logic.

Let the synthesis tool take care of all the low-level details for you!

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  • \$\begingroup\$ Some real 74xx parts offer behaviors that are from what I can tell rather hard to code in Verilog/VHDL. For example, a 74LS74 can guarantee that if the output and data input are high, transitions on the clock or "set" inputs--even near-simultaneous ones--won't glitch the output, and likewise if the output and data input are stable low. I'm not sure how one could let the synthesis tool take care of requirements that can't be specified in the language. \$\endgroup\$
    – supercat
    Feb 3, 2016 at 17:29
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    \$\begingroup\$ @supercat: That's an issue related to the underlying FPGA's actual FFs, and has nothing to do with the (presumed) synchronous logical design of the overall circuit. A dependence on glitch-free behavior means that your circuit is sensitive to glitches in the first place -- something that is to be avoided in general. \$\endgroup\$
    – Dave Tweed
    Feb 3, 2016 at 17:38
  • \$\begingroup\$ How would one avoid sensitivity to glitches if e.g. an FPGA is being used to generate a clock signal for an off-board chip and output clock pulses won't always be synchronous to the same input source? \$\endgroup\$
    – supercat
    Feb 3, 2016 at 18:30
  • \$\begingroup\$ @supercat: Again, that's a question that's related to the specific FPGA technology being used. But in general, one uses the DDR features of the I/O pad drivers to create clean output clocks that have well-controlled skew, etc. with respect to the corresponding data lines. All of the pads in the group are driven by a clock inside the FPGA that has been cleaned up by a PLL or DCM. If you have a specific scenario in mind, perhaps you should ask a separate question. \$\endgroup\$
    – Dave Tweed
    Feb 3, 2016 at 18:35
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If you really want to take your hands of the keyboard often, then quartus has a symbolic editor with gates already made. Video Example. I'm sure some of the other synthesis tools have symbolic editors like this but it is so much easier to code it in with verilog or vhdl.

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