1
\$\begingroup\$

I am new to Virtex 5 which has an embedded PPC440 core in it (XC5VFX70T). I am using the Xilinx ML507 board for my design.

I created the embedded core using XPS and instantiated it in my HDL project. As peripherals, I am using a DDR2 controller, BRAM, SRAM, one UART and a few GPIOs. However, I could not see any address/data bus ports from the embedded core which I can use in the FPGA fabric.

I have a few RTL IP cores which require memory mapping. How do I connect these IP cores to PPC440 core? Also there are a few registers implemented in the FPGA fabric which are used for system initialization. I want the PPC440 core to write to these registers during initialization. How can I achieve this if the embedded core doesn't have address/data bus as external ports?

\$\endgroup\$

1 Answer 1

1
\$\begingroup\$

Take a look at Xilinx UG200 and the MPLB interface. This looks like the port that you will need to connect your memory mapped peripherals to, probably with a decent amount of interface logic.

\$\endgroup\$
2
  • \$\begingroup\$ I will try that. Should I define it as a custom peripheral and connect it to MPLB? I guess I will have to develop the drivers for custom peripherals also. \$\endgroup\$
    – matryx
    Commented Feb 9, 2016 at 8:12
  • \$\begingroup\$ Yeah, I think so. I presume you just implement the peripherals in HDL and then connect them to the ppc440 instance. As far as the software goes, I think it just ends up being memory mapped somewhere. I'm not sure how much flexibility there is as far as configuring that. I have never used the ppc cores in a design before. \$\endgroup\$ Commented Feb 9, 2016 at 9:33

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.