ECL has got a really bad rap among people who never used it, when in fact it is perhaps the easiest to use of all logic families when static power is of no concern, and has an excellent delay-power product (the delay through a gate multiplied by the static power dissipation). It also produces comparably little supply plane noise, and in many designs the distributed capacitance of the closely-spaced power planes will be sufficient to decouple the 10k family - with no extra capacitors! (But not the III/10H/100H).
By following rather basic guidelines it's easy to make it work reliably and without much fuss. In practice, all you need to know is that:
Several modern(ish) ECL families are I/O compatible, e.g. at the very least the 10k, 100k, MECL III, 10H and 100H families. The 10k family is the most docile one, with intentionally detuned transition times to make it easier to work with - slower in general than 10H. 10H is faster, and has better logic level compensation vs. process and supply voltage.
MECL III is the in-between family: faster than 100k, but slower than 10H. As a rule of thumb, MECL III halves the propagation delay of 10k, and 10H halves that yet again.
The 100"k" series in general add further temperature compensation to their respective 10"k" counterparts - without any speed changes, providing the most "accepting" of inputs (in terms of proper operation given inaccurate input logic levels), and most stable output logic levels. But, since 10k was a transition-detuned family, 100k also gets rid of this detuning, making the edge transition times faster than 10k. The propagation delays are not affected, just as they aren't when you move from 10H to 100H.
There's no separate PECL family: it's simply ECL operated from 0V/5V supplies vs -5V/0V. The logic levels differ between the two, since they are referenced to the higher voltage. So, [N]ECL logic levels are 0V-referenced, and PECL is 5V-referenced. In modern systems, PECL would be the way to go since negative supplies not normally present in digital systems.
In practical terms, every digital line driven by ECL has to be terminated in its characteristic impedance. Single-ended lines are terminated to a termination voltage plane. Thus, for PECL, you'd use three power planes: Vcc=+5V, Vtt=Vcc-2V=+3V, and Vee=0V. A differential pair has to be diferentially terminated in its characteristic differential impedance, and the driver end needs pulldowns to Vee. The termination mismatch encountered in typical designs incurs a few percent reflection, and is usually inconsequential.
Note that all ECL AC specs are usually given assuming 50 Ohm termination; higher termination values detune the fall times and make rise/fall asymmetric.
ECL has practically unlimited fan-out. For example, typical 10k family fanout is 90+ loads, MECL III fanout is 60+. As you increase the load count, you'll run into slew rate and impedance control issues way before you hit the maximum dictated by the fan-out. In practice, fan-outs of 5-10 are reasonable.
ECL has open-emitter outputs and thus you can wire-OR signals. OR-ing PTERMS is free in ECL. Wire-OR capacity is independent of fanout and is limited only by capacitive loading and impedance matching.
ECL circuitry always generates complementary outputs. Sometimes they may not be provided by the chip, but typically they are. Those outputs have inherently very low skew.
10k ECL can be wire-wrapped, using DIP packages (!!) on a suitable wire wrap board with tightly coupled power planes, and it's not terribly difficult to put together 100MHz-clocked "wide" (parallel data paths) designs using wire wrap and DIP packages exclusively.
The seminal reference for homebrew ECL, wire-wrapped, 10k-family-based design is Hastings, Chuck*. (1978). A Recipe for Homebrew ECL. Computer Music Journal. 2. 10.2307/3680138. The venue of publication may seem odd, if it wasn't for Mr. Hasting's interest in music; it's easy to imagine that he saw high-performing DSP as an inroad to digital music synthesis. The abstract reads:
Emitter-coupled logic (ECL) is understood by most computer designers to be the fastest stuff available, which it is - and as too difficult for anyone but the largest companies to design with, which it isn't! If an appropriate recipe is followed, ECL systems can be developed with very limited resources with as good, or better, chances of technical success as with equivalent TTL systems. Thus, homebrew ECL is a serious possibility for applications which need the speed. Such applications may occur in some technical approaches to music synthesis, speech analysis, and personal scientific computing involving matrices or partial differential equations.
Such a recipe isn't written down anywhere - existing ECL tutorials make ECL design sound formidable. However, a careful amateur can achieve a reliable 100 MHz small system today if he knows what to do. This paper will present a practical recipe, used once successfully, for designing, building, and troubleshooting a small ECL system with the level of resources available in a well-equipped homebrew lab.
This recipe was developed during the course of one task in a project at Racal-Milgo, a medium-sized Florida company with no previous ECL systems experience. The circumstances were in many ways quite similar to those of a homebrew project. The outcome of the task was a 24-bit general-purpose stored-microprogram computer, capable of 6,000,000 three address fixed-point add/subtract/Boolean instructions or 900,000 fixed-point multiply instructions per second, which was completed and has since been operated 10 hours a day for several months in a signal-processing system.
Of course nobody manufactures DIP-packaged ECL anymore, but you could have some fun putting together e.g. a 16-bit counter that runs off a 500MHz clock using secondhand parts. In wire wrap. This is very hard to achieve, if at all possible, using any TTL or CMOS family, even if they were fast enough and available in DIP package. If that's not an argument for the versatility of ECL, I don't know what is. Moreover, small ECL circuits with differential signaling can be put together in a pinch on a solderless breadboard - e.g. a 0.5GHz ring oscillator, with a subsequent prescaler to allow you to actually measure the frequency using something more practical. This particular experiment may not endear you to other users of the radio spectrum, but it fundamentally works. If DIP packaged ECL was a thing, I'd rather be using that instead of TTL when I do simple logic demos. Cranking the speed "to 11" is a cool parlor trick, given a sufficiently swell parlor ;)
10H/100H can be point-to-point wired (not wire-wrapped) on a dedicated protoboard that includes distributed decoupling capacitances and a provision for surface-mount terminators to either Vtt or Vee at any pin of the package (to account for pull-downs on differential lines). Such boards were never available for sale as far as I know, but are a simple matter if you were to custom-design one - and you'd need it for any serious hand-wired work with those faster families.
As a matter of reference, an ECL 10k implementation of something like the groundbreaking ADSP2100, running faster than the original, would be probably <1k of ECL chips if given enough money for the various state-machine RAMs it would need - in times when you could get them, that is. And quite possibly wire-wrapped :) I imagine that Mr. Hasting's 6MIPS machine had to be cost-constrained, and he couldn't e.g. use "large" (64kbits) ECL SRAM to squeeze gobs of low-integration logic into single-chip look-up tables.
Impedance-wise, suppose we have a 4-layer 0.062" board thickness stackup from Bay Area Circuits - nothing special about it, just that it stands for something concrete, and we use the Saturn PCB Design toolkit to calculate trace impedances. The core and prepreg have dielectric constant of 4.6. All of the following concrete values are valid only to the stackup mentioned.
A single trace on the outer layer over the power or ground plane is called a microstrip, and a 13mil trace will have a 50 Ohm impedance, but tight matching requires impedance control in the manufacturing process. Without it - it's a matter of chance, and some variation is to be expected. A 10 mil trace has Z0=57 Ohm, and a 7mil trace has Z0=66 Ohm. Maintaining a constant trace width, short stub length (for fanout > 1), and parallel-terminating at the far end of the line (away from the output) is what you'd do. As long as you do that, everything will work as expected.
For edge-coupled differential microstrip on the same board, a 10 mil trace / 10 mil space pair has the differential impedance of ~94 Ohms, and the far end termination resistor would be applied not from each trace to Vtt, but between the traces, i.e. a differential termination equal in value to differential impedance. The driven ends would have 500Ohm pulldowns to Vee (0V) since the logic is open-emitter.
* Chuck Hastings passed away on 4/2/2018. He was a rather prolific engineer.