I was reading the comments to this question Can I replace a PLL Charge Pump with an Active LPF? and started looking at the MCH12140 and MC10EL07 that markrages♦ recommended.

When I look at the datasheet it talks about MECL 10h and 1000 K ECL logic levels. What does that mean? How can I use it?

Note, I did try to google what the MECL and ECL was, but either I wasn't using good search terms or it is just hard to find. There is pages on them, but nothing talks about 10h and 1000 k. I also don't really understand what the pages mean.

Also note that I have used TTL before, is there any comparison to TTL or a way to convert to it?


To get straight to the question asked, you can find the logic levels for 10H or 100H logic by going to any datasheet for a part in those families. On Semi is the main vendor for those parts (though Fairchild and other vendors have second-sourced them as well), and you can get a list of all the parts in the family here.

One thing to be aware of is that ECL logic levels are referenced to VCC rather than VEE, so the logic level will be something like Vih ~= Vcc-1 and Vil ~= Vcc - 1.7. For the full range of mins and maxes for the input and output levels, check an actual datasheet.

A previous answer stated that ECL logic is "a differential logic standard." While most ECL parts use differential inputs and outputs, many complex functions, especially in the earlier generations, were built with single-ended i/o's.

It was also stated that ECL runs "much faster than TTL, and draws more power". While its typically true that ECL will draw more power for a gate that doesn't switch often, the power draw of ECL doesn't increase as much as TTL when the switching frequency goes up. So there's typically some frequency above which ECL will actually draw less power than the same function in TTL.

Another issue to watch out for is that MECL parts date from the era when engineers designed from paper data books, rather than downloading data sheets part-by-part off the net. Some of the characteristics of these parts were only described in the introductory chapters of the databook, and not in the individual parts' datasheets. (For example, the pin-outs for certain packages were not in each datasheet, but a translation table from DIP pins to pin #'s for other packages was included in the introduction.) I think that most of this information can nowadays be found in the App Note "General Information for MECL 10H and MECL 10K".

There was once upon a time an excellent "Design Handbook" for using the MECL parts that had lots of information on controlled impedance design, differential logic design, etc., that is still relevant today...sadly I can't seem to find this handbook online at the moment.


Majenko has linked to the Wikipedia article, but in a nutshell (thanks to The Photon for corrections):

  • ECL is typically used as differential logic, meaning that a logic value is sent over two complementary lines. One line is the "positive" polarity, the other is inverted.
  • ECL is designed to run much faster than TTL, and can draw more power. Edge rates and propagation delays are around 1 ns, so high-frequency considerations are necessary. You have to pay attention to termination as well.
  • ECL operates with supplies at -5V and 0V, in contrast to TTL. ECL also specifies an additional supply for \$V_{TT}\$, the termination voltage supply, though you can sometimes get away without this.
  • You can run most ECL parts in PECL ("positive ECL") mode, using 0V and +5V supplies, and positive \$V_{TT}\$.
  • ECL has a specific requirements for power supplies and logic thresholds. The various 10x families are slightly different. The 100 parts are apparently just temperature compensated.

ECL is high-performance stuff, so if you do anything serious with it, I really recommend reading the documentation. In particular, OnSemi app notes TND309 and AN1406. There's a lot of details, especially regarding termination.

For this project, though, I can give some rough guidelines.

PECL example

Here's an excerpt from a board I made. The '57 is a mux, connected in PECL mode. You can see how there's no \$V_{TT}\$ anywhere. The Q+/Q- pair is connected to ground through 200 ohm resistors on the driving side. The D pairs on the receive end are terminated with 100 ohm resistors.

So you could run the U and D pairs into two MC100ELT25's, with appropriate resistors. Another option is the SN65LVDS34D, which has integrated termination resistors, but it's a slower part. If you put all the chips right next to each other, you won't need to worry about transmission-line effects.


ECL has got a really bad rap among people who never used it, when in fact it is perhaps the easiest to use of all logic families when static power is of no concern, and has an excellent delay-power product (the delay through a gate multiplied by the static power dissipation). It also produces comparably little supply plane noise, and in many designs the distributed capacitance of the closely-spaced power planes will be sufficient to decouple the 10k family - with no extra capacitors! (But not the III/10H/100H).

By following rather basic guidelines it's easy to make it work reliably and without much fuss. In practice, all you need to know is that:

  1. Several modern(ish) ECL families are I/O compatible, e.g. at the very least the 10k, 100k, MECL III, 10H and 100H families. The 10k family is the most docile one, with intentionally detuned transition times to make it easier to work with - slower in general than 10H. 10H is faster, and has better logic level compensation vs. process and supply voltage.

    MECL III is the in-between family: faster than 100k, but slower than 10H. As a rule of thumb, MECL III halves the propagation delay of 10k, and 10H halves that yet again.

    The 100"k" series in general add further temperature compensation to their respective 10"k" counterparts - without any speed changes, providing the most "accepting" of inputs (in terms of proper operation given inaccurate input logic levels), and most stable output logic levels. But, since 10k was a transition-detuned family, 100k also gets rid of this detuning, making the edge transition times faster than 10k. The propagation delays are not affected, just as they aren't when you move from 10H to 100H.

  2. There's no separate PECL family: it's simply ECL operated from 0V/5V supplies vs -5V/0V. The logic levels differ between the two, since they are referenced to the higher voltage. So, [N]ECL logic levels are 0V-referenced, and PECL is 5V-referenced. In modern systems, PECL would be the way to go since negative supplies not normally present in digital systems.

  3. In practical terms, every digital line driven by ECL has to be terminated in its characteristic impedance. Single-ended lines are terminated to a termination voltage plane. Thus, for PECL, you'd use three power planes: Vcc=+5V, Vtt=Vcc-2V=+3V, and Vee=0V. A differential pair has to be diferentially terminated in its characteristic differential impedance, and the driver end needs pulldowns to Vee. The termination mismatch encountered in typical designs incurs a few percent reflection, and is usually inconsequential.

    Note that all ECL AC specs are usually given assuming 50 Ohm termination; higher termination values detune the fall times and make rise/fall asymmetric.

  4. ECL has practically unlimited fan-out. For example, typical 10k family fanout is 90+ loads, MECL III fanout is 60+. As you increase the load count, you'll run into slew rate and impedance control issues way before you hit the maximum dictated by the fan-out. In practice, fan-outs of 5-10 are reasonable.

  5. ECL has open-emitter outputs and thus you can wire-OR signals. OR-ing PTERMS is free in ECL. Wire-OR capacity is independent of fanout and is limited only by capacitive loading and impedance matching.

  6. ECL circuitry always generates complementary outputs. Sometimes they may not be provided by the chip, but typically they are. Those outputs have inherently very low skew.

  7. 10k ECL can be wire-wrapped, using DIP packages (!!) on a suitable wire wrap board with tightly coupled power planes, and it's not terribly difficult to put together 100MHz-clocked "wide" (parallel data paths) designs using wire wrap and DIP packages exclusively.

The seminal reference for homebrew ECL, wire-wrapped, 10k-family-based design is Hastings, Chuck*. (1978). A Recipe for Homebrew ECL. Computer Music Journal. 2. 10.2307/3680138. The venue of publication may seem odd, if it wasn't for Mr. Hasting's interest in music; it's easy to imagine that he saw high-performing DSP as an inroad to digital music synthesis. The abstract reads:

Emitter-coupled logic (ECL) is understood by most computer designers to be the fastest stuff available, which it is - and as too difficult for anyone but the largest companies to design with, which it isn't! If an appropriate recipe is followed, ECL systems can be developed with very limited resources with as good, or better, chances of technical success as with equivalent TTL systems. Thus, homebrew ECL is a serious possibility for applications which need the speed. Such applications may occur in some technical approaches to music synthesis, speech analysis, and personal scientific computing involving matrices or partial differential equations.

Such a recipe isn't written down anywhere - existing ECL tutorials make ECL design sound formidable. However, a careful amateur can achieve a reliable 100 MHz small system today if he knows what to do. This paper will present a practical recipe, used once successfully, for designing, building, and troubleshooting a small ECL system with the level of resources available in a well-equipped homebrew lab.

This recipe was developed during the course of one task in a project at Racal-Milgo, a medium-sized Florida company with no previous ECL systems experience. The circumstances were in many ways quite similar to those of a homebrew project. The outcome of the task was a 24-bit general-purpose stored-microprogram computer, capable of 6,000,000 three address fixed-point add/subtract/Boolean instructions or 900,000 fixed-point multiply instructions per second, which was completed and has since been operated 10 hours a day for several months in a signal-processing system.

Of course nobody manufactures DIP-packaged ECL anymore, but you could have some fun putting together e.g. a 16-bit counter that runs off a 500MHz clock using secondhand parts. In wire wrap. This is very hard to achieve, if at all possible, using any TTL or CMOS family, even if they were fast enough and available in DIP package. If that's not an argument for the versatility of ECL, I don't know what is. Moreover, small ECL circuits with differential signaling can be put together in a pinch on a solderless breadboard - e.g. a 0.5GHz ring oscillator, with a subsequent prescaler to allow you to actually measure the frequency using something more practical. This particular experiment may not endear you to other users of the radio spectrum, but it fundamentally works. If DIP packaged ECL was a thing, I'd rather be using that instead of TTL when I do simple logic demos. Cranking the speed "to 11" is a cool parlor trick, given a sufficiently swell parlor ;)

10H/100H can be point-to-point wired (not wire-wrapped) on a dedicated protoboard that includes distributed decoupling capacitances and a provision for surface-mount terminators to either Vtt or Vee at any pin of the package (to account for pull-downs on differential lines). Such boards were never available for sale as far as I know, but are a simple matter if you were to custom-design one - and you'd need it for any serious hand-wired work with those faster families.

As a matter of reference, an ECL 10k implementation of something like the groundbreaking ADSP2100, running faster than the original, would be probably <1k of ECL chips if given enough money for the various state-machine RAMs it would need - in times when you could get them, that is. And quite possibly wire-wrapped :) I imagine that Mr. Hasting's 6MIPS machine had to be cost-constrained, and he couldn't e.g. use "large" (64kbits) ECL SRAM to squeeze gobs of low-integration logic into single-chip look-up tables.

Impedance-wise, suppose we have a 4-layer 0.062" board thickness stackup from Bay Area Circuits - nothing special about it, just that it stands for something concrete, and we use the Saturn PCB Design toolkit to calculate trace impedances. The core and prepreg have dielectric constant of 4.6. All of the following concrete values are valid only to the stackup mentioned.

A single trace on the outer layer over the power or ground plane is called a microstrip, and a 13mil trace will have a 50 Ohm impedance, but tight matching requires impedance control in the manufacturing process. Without it - it's a matter of chance, and some variation is to be expected. A 10 mil trace has Z0=57 Ohm, and a 7mil trace has Z0=66 Ohm. Maintaining a constant trace width, short stub length (for fanout > 1), and parallel-terminating at the far end of the line (away from the output) is what you'd do. As long as you do that, everything will work as expected.

For edge-coupled differential microstrip on the same board, a 10 mil trace / 10 mil space pair has the differential impedance of ~94 Ohms, and the far end termination resistor would be applied not from each trace to Vtt, but between the traces, i.e. a differential termination equal in value to differential impedance. The driven ends would have 500Ohm pulldowns to Vee (0V) since the logic is open-emitter.

* Chuck Hastings passed away on 4/2/2018. He was a rather prolific engineer.


Here is an unencumbered version of (1978). A Recipe for Homebrew ECL. Just read it, pretty fair.



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