The problem statement is not exactly on synthesizing circuit but in one of the interim steps that I am trying to learn.
1) In order to design a sequence detector in Verilog (using structural modeling) I was learning to synthesize digital circuit first and stumbled upon a tutorial which I could relate to my problem as given here:-
2) Everything was smooth sail until I came across this section on the page numbered 273 (5th page of the document). Attaching the snapshot of the dubious section
3) What I could not understand is the 'Match' Row below the truth table. My initial impression was some sort of reduction from K-map; but either it isin't or my method of doing it wasn't correct.
4) In all likelihood it may be some other silly thing that I may be totally ignoring, but just to support my point, I have only started to 'make it all work together'
Any help will be highly appreciated.