The problem statement is not exactly on synthesizing circuit but in one of the interim steps that I am trying to learn.

Problem Statement.

1) In order to design a sequence detector in Verilog (using structural modeling) I was learning to synthesize digital circuit first and stumbled upon a tutorial which I could relate to my problem as given here:-

2) Everything was smooth sail until I came across this section on the page numbered 273 (5th page of the document). Attaching the snapshot of the dubious section

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3) What I could not understand is the 'Match' Row below the truth table. My initial impression was some sort of reduction from K-map; but either it isin't or my method of doing it wasn't correct.

4) In all likelihood it may be some other silly thing that I may be totally ignoring, but just to support my point, I have only started to 'make it all work together'

Any help will be highly appreciated.


1 Answer 1


Yes, the "Match" row gives the logical expressions that match the table data immediately above. Keep in mind that the table is not showing all of the possible values for "PS" (present state), and the missing rows are being treated as "don't cares" when creating the expressions.

For example, here's the part of the table for Y2, showing the missing rows, and replacing the X values with values that show how the expression below works.

PS      Next State
Y2Y1Y0   X=0  X=1
 0 0 0   0    0
 0 0 1   0    0
 0 1 0   X(1) X(0)
 0 1 1   1    0
 1 0 0   0    1
 1 0 1   0    0
 1 1 0   X(1) X(1)
 1 1 1   X(1) X(0)

 Match   Y1   Y2*Y0'

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