# Pin Assignment in ispLEVER Classic

I have an ispGAL22LV10C that I'm trying to program. I wrote and synthesized the VHDL in ispLEVER Classic, but I cannot seem to figure out how to create pin assignments. Documentation on this is kind of lacking, how might I go about this? I cannot seem to find this fabled "constraint editor" in my version (the latest). Thanks

Found it on my own after an hour of searching. As per the website:

# How can I assign device pin out for GAL devices?

The Design Planner (or the Constraint / Preference Editor) is not supported for GAL devices. The pin assignments can be made either in the HDL source code itself or you can let the software choose them.

For ABEL, specify a pin number when declaring the pin.

Example syntax for ABEL source pin assignments can be found in File > Open Examples. Then browse to Examples > SPLD > gal > mlcount > mlcount

For VHDL or Verilog, use the attribute 'LOC'

Below is an example in VHDL:
Syntax

attribute LOC : string;
attribute LOC of SigName: signal is "P[Pin#]";


Example

attribute LOC : string;
attribute LOC of out0: signal is "PA3";
attribute LOC of out1: signal is "PF8 PA2 PB3";

• This seems to work with "simple" signals. The problem I have is when I want to assign vector members: attribute LOC of A(15):signal is "P15";. In such case I get @E: CD128 :"C:\users\public\documents\isplever\design.vhd":28:18:28:18|Expecting : before class of object(s). Any help with that? – silverdr Mar 13 '18 at 9:53

I have found a different solution (with at least ABEL_Schematic):

In the 'Chip Report' there is a line with 'ABEL PLA file'. Find that file in your design directory and inside you will find the following line

#\$ PINS .....


now here you can reassign the pins like "A11:13 A12:15 "..etc {signal name}:{pin#}

After done, just run the 'Fit design' (+create fuse map) again and voila, you have the right signals at the right place.