Sharing output of module in verilog

Having started to learn Verilog there was this doubt that crept my mind which is as follows:-

1) Consider the following Verilog code with 3 modules. Module 'Clock' that simulates a clock, module D Flip Flop and module JK Flip Flop:-

module clock(clock_out); //Clock Module
output clock_out;
reg clk;
wire clock_out;
assign clock_out=clk;
initial
clk=1'b0;
always
begin
#200    clk=~clk;
end
endmodule

module d(q,q1,d,c); //D Flip Flop
output q,q1;
input c,d;
wire c;
clock clock1(.clock_out(c)); //clock module instantiated
reg d;
reg q,q1;
initial
begin
q=1'b0; q1=1'b0;d=1'b0;
end
always @ (posedge c)
begin
q=d;
q1= ~d;
d=~d;
end
endmodule

module jk(q,q1,j,k,c);   //JK Flip Flop
output q,q1;
input j,k,c;
reg q,q1;
wire c;
clock clock2(.clock_out(c));// another clock module instatiated

initial begin q=1'b0; q1=1'b1; end
always @ (posedge c)
begin
case({j,k})
{1'b0,1'b0}:begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=~q; q1=~q1; end
endcase
end
endmodule


2) In this setup having instantiated a clock module each in the D and JK Flip Flop module can I expect the clock (output signal generated by module clock) in sync in both these modules or should I expect a lag equal to the delay of actual instantiation of the clocks when the simulation started?

PS: Please let me know if I have not been able to explain myself. Didnt want to lengthen the post than required.

Your first problem is here:

module d(q,q1,d,c); //D Flip Flop
output q,q1;
input c,d;           // Line A
// ...
always @ (posedge c)
begin
q=d;
q1= ~d;
d=~d;       // Line B
end
endmodule


If you make d an input to a module (in line A), you should not be driving it like you are in line B. The inputs to d should be driven by something in the upper-level module that instantiates d.

(You also assign an input of the d module when you instantiate a clock within it and connect the clock's output to an input signal.)

Your second problem is that you defined three modules, but you never instantiated them anywhere. You need to make a "main" or "top_level" module that instantiates at least one instance of each of your sub-modules, and tells how they're connected to each other.

In this setup having instantiated a clock module each in the D and JK Flip Flop module can I expect the clock (output signal generated by module clock) in sync in both these modules or should I expect a lag equal to the delay of actual instantiation of the clocks when the simulation started?

They will be in sync, but only because the simulator is idealized. All initialization happens effectively at the same time. However, your clock module is not synthesizable code, because it relies on a magical "#200" delay without any indication how that would be produced in a physical circuit.

So, in simulation, your two modules (if you actually instantiated them somewhere) would operate in sync. But the usual way to do things is to make a main module, instantiate one clock module there, and use its output as the c input for instances of the two flip-flop modules. (If you actually made clock to be a synthesizable design, this would also save resources by not creating two copies of it when you only need one)

• Thanks a lot!! Things are a lot clearer now. You say "If you actually made clock to be a synthesizable design, this would also save resources by not creating two copies of it when you only need one". Even in the non synthesizeable code above, are we not supposed to create just one clock module and pass its output as inputs to the two other module? Also can a testbench act as the 'main module', lets say if I only need to simulate and not synthesize ? Commented Feb 7, 2016 at 2:19
• Yes, that's a better way to model a real circuit. Commented Feb 7, 2016 at 2:21