# Mathematical Logic behind generating T0 codes

I'm doing a small project in college where I'm required to convert(encoding) between gray and binary codes and also for bus invert coding in verilog. Its a simple task really as I'm done with code for the above said encoding methods.

Now to the point, I'm required to generate T0 codes from either binary or gray format. I've hit a stumbling roadblock trying to understand what is this T0 code all about. Rummaging through the internet, I could only find journals that offer only a vague outline about this kind of code.

I'm really good at coding and all I need to know is if it is possible to encode a binary input code to a T0 code or vice versa. If so, I would like to know the mathematical logic or steps performed for generating them. Note that this is just a mini project done just to get the hang of digital logic as part of my university's curriculum.

If the above is not feasible, care to suggest an alternate encoding technique

• Everything You should know is here: sapub.org/global/showpaperpdf.aspx?doi=10.5923/… At section 4. there is even a pseudo-code showing how to convert binary code into T0 code. Feb 7, 2016 at 22:04
• @lustful-rat, Thanks for the info. But I can't relate the pseudo-code for a given input bit stream or maybe I just didn't understand it. Would you care to simplify it a little bit by giving an example? Feb 8, 2016 at 6:18

According to the paper found by @lustful-rat, T0-C is not a method for encoding binary words individually, but rather a method of encoding sequences of binary words. It is used in situations in which the sequences frequently contain groups of values that are a fixed offset from each other, such as stepping through a memory array by bytes or words.

The transmitter and receiver agree on a step size $S$. If the next value to be transmitted is the previous value plus S (i.e., $b(t) = b(t-1) + S$), then the actual value on the bus is not changed ($B(t) = B(t-1)$). Otherwise, the next value is placed on the bus ($B(t) = b(t)$).

However, there is a problem: What if the next value to be transmitted is not the previous value plus S, but it happens to be the same as the current value on the bus ($b(t) = B(t-1)$)? In that case, there is only one value that the receiver should NOT be expecting to see, and that is $b(t-1) + S$, because if that really were the value to be transmitted, the transmitter would simply keep the bus at $B(t-1)$. So if the transmitter actually puts that value on the bus, then the receiver knows that this is a special case, and that $b(t)$ should now be set to $B(t-1)$.

As long as the sequence of values frequently contains sequential values, this method reduces power consumption by greatly reducing the number of transitions on the individual bus wires. In order to implement it, both the transmitter and the receiver need to keep track of $b(t-1)$ and $B(t-1)$ internally, so that the logic described above (and in the paper) can be constructed.

Transmitter                        Receiver
-----------                        --------
Inputs: b(t-1), b(t), B(t-1)       Inputs: b(t-1), B(t-1), B(t)
Output: B(t)                       Output: b(t)

if (b(t) == b(t-1)+S)              if (B(t) == B(t-1))
B(t) = B(t-1)                      b(t) = b(t-1) + S
else if (b(t) == B(t-1))           else if (B(t) == b(t-1)+S)
B(t) = b(t-1)+S                    b(t) = B(t-1)
else                               else
B(t) = b(t)                        b(t) = B(t)

• What does Step Size S mean? Feb 29, 2016 at 4:08
• S is the difference between one memory address and the next. For example, if memory is byte addressable, but organized as 32-bit words, S would be 4. Feb 29, 2016 at 11:56