I am trying to understand the physical phenomenon that leads to increase in gain of an amplifier as the output impedance increases.

When we have resistive loads in a single stage amplifier, they convert the signal current change into voltage variation. Higher the value of load, more will be the conversion and hence the gain. In MOSFETs, since it is not necessary for the output impedance to be less, higher gain can be obtained by increasing the RD**(physical resistance connected to drain)** while ensuring that the transistor operates in saturation.

But how does increasing the rds(the internal drain-source resistance) help obtain higher gain? Since rds is not a physical resistor, how does it contribute to increase in gain?

By using long channel MOS, the rds could be increased. This would mean, lesser current variation in saturation region with change in Vds. When we model the effect of channel length modulation, we of course obtain a resistor of higher value.

Can anyone explain me how does the change in length could increase the gain?


I have edited the question and included correct notation for small signal dynamic resistance.

I understand that rds is not an actual resistor but a model that takes into account the effect of channel length modulation. But then how does it increase the gain of the amplifier?

Higher rds would mean small change in drain current for Vds variation i.e., a good current source. That is all I can gather from this model.

My question however is that how would this increase the intrinsic gain of the amplifier? I understand how gain increases as RD increases(which I have mentioned above). Am I correct?


2 Answers 2


Like LvW says in his answer, note that what we call Rds is not a physical resistor present in the MOSFET but it is a phenomenon which is presented by a resistor called Rds in the small signal model of the MOSFET.

You take a MOSFET, you apply DC voltages and currents to it so that it will have a certain operating point. For example, an operating point where the drain current Ids = 1 mA and Vds is 3 V. For this imaginary NFET Vt = 1 V so this NMOS is in saturation.

Now that we know the operating point of this NMOS, we can calculate values for some small signal parameters of this NMOS at this operationg point. These parameters are all derivatives For example:

$$gm = dId / dVgs$$


$$Rds = dVds / dId$$

Note how Rds is the derivative of Vds/Id !

The values of gm and Rds result from the physical properties of the MOSFET. So for a different MOSFET (for example, one with a longer channel) these values will be different. In general, Rds will be larger for a MOSFET with a longer channel.

But this does not explain yet why this is so.

What does explain it is the Channel length modulation effect. For MOSFETs with very short channels the drain is (physically close to the part of the MOSFET's channel which determines the drain current when it is in saturation. As the voltage on the drain increases the depletion layer around the drain also increases in size. Worst case this depletion region can even touch the channel. This results in a low ohmic path between drain and source and Rds will be very low.

If the drain is physically further away from the source that depletion region cannot get anywhere near the channel so the channel will determine the current without the drain and it's depletion region interfering. This results in a more ideal current source behavior of the channel. For a high Rds, this is what is needed, it means dId will be very small (only small drain current variations due to changes in Vds).

  • \$\begingroup\$ For my opinion, it would be helpful to discriminate between STATIC and DYNAMIC resistances - and to use, therefore, upper case (R) for static and lower case (r) for dynamic/diff. resistances. \$\endgroup\$
    – LvW
    Feb 8, 2016 at 9:58
  • \$\begingroup\$ I agree, that is the normal convention. I stuck with capitals here so that its a bit easier to read. But you're correct, lowercase is the official notation. \$\endgroup\$ Feb 8, 2016 at 10:07
  • \$\begingroup\$ Thank you! I understand how the change in length would result in variation of resistance between drain and source. When we model the channel length effect as a resistor rds, that would lead in increased output impedance. But current doesn't actually flow through this. (That is just a model). How this would increase the gain? Please check the edit. \$\endgroup\$
    – JGalt
    Feb 8, 2016 at 14:59
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    \$\begingroup\$ The small signal part of the drain current does flow through Rds (assuming there is only a DC current source connected to the drain) ! The (small signal) gain of a common-source stage is: gm * Rds. Where gm is the amount of current change due to a change in Vgs (again, small signal !) These current variations are then fed into the small signal impedance at the drain. If the drain current is supplied by an ideal current source then the only impedance at the drain is Rds. So gm * Rds = voltage gain Hence larger Rds will give larger voltage gain. \$\endgroup\$ Feb 8, 2016 at 15:05
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    \$\begingroup\$ You nailed it ! :-) \$\endgroup\$ Feb 8, 2016 at 18:33

What do you mean with RDS? Ohmic resistance between D and S in the linear region of the FET? I don`t think so. Speaking about gain you you certainly mean the dynamic resistance rds, correct? This is a resistance determined by the slope of the output characteristics Id=f(Vds).

Knowing that the transistor works as a (non-ideal) controlled current source this source can be seen as an ideal source in parallel with this resistance rds. Hence, the effective resistance at the drain node is RD||rds.

(Please note, that it is always good and necessary to discriminate between an ohmic resistor R and a differential/dynamic resistance r).

  • \$\begingroup\$ Thank you. I was talking about the small signal dynamic resistance rds and not the actual RD. Could you please have a look at the edited question? \$\endgroup\$
    – JGalt
    Feb 8, 2016 at 14:57
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    \$\begingroup\$ If you analyze the output characteristics Id=f(Vce) in the saturation region you can define and measure the ratio d(Vds)/d(Id). This is the dynamic resistance of the D-S path. \$\endgroup\$
    – LvW
    Feb 9, 2016 at 10:15

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