I'm concluding my two-layer PCB design and my last obstacle is ground planes.

Specifically, the problem is the TPS63060 IC that requires Power Ground separation from Control Ground (pin 7). That is a 2.2 MHz max buck/boost regulator that will actually operate between 3.3-7V

The datasheet states:

My design looks pretty the same but I don't understand how to predict the path of the Control Ground return current.

On the basis of what I understood, C2, C3, R2 grounds are connected on that island, then they are switched on the bottom plane. The return current, however, should return to the device's ground that sends that VIN. But return current could simply pass through thermal vias and come back to the top ground plane and follow an unexpected path: the Power Ground path.

Thank you ;)

  • \$\begingroup\$ Is this a two layer design? What is this chip? Which pins are the control ground? \$\endgroup\$
    – Voltage Spike
    Feb 8, 2016 at 17:14
  • \$\begingroup\$ I'm sorry for the missing informations. I'll add them in the question. \$\endgroup\$
    – Nic1337
    Feb 8, 2016 at 17:28
  • \$\begingroup\$ Added extra informations. \$\endgroup\$
    – Nic1337
    Feb 8, 2016 at 17:41
  • 1
    \$\begingroup\$ Are you planning to make the bottom side mostly a solid GND plane? Are you placing components on the bottom side, or all components on the top side? Note that in the reference design, the control GND is connected to the thermal GND pad, but you didn't do that. You should do that. Also note that in the reference design, it is clearly assumed that the bottom side is a GND plane, and this is important. If you are not planning to do that, I think you need to make some changes. \$\endgroup\$
    – user57037
    Feb 8, 2016 at 18:47
  • 1
    \$\begingroup\$ I am concerned about the the ground-plane under your inductor. Remember that the inductor is coiled "horizontal" to the PCB's plane, so there will be a huge magnetic field under the footprint. I'd recommend staying away completely under the inductor, which is also indicated by the reference design. \$\endgroup\$ Feb 8, 2016 at 19:39

1 Answer 1


I'll take a stab at this real quick, though it can be a fairly complex question. Manufacturers are often quite bad at communicating what they mean by 'separating the grounds', and the piles of application notes of varying quality do not help that mess.

Basically, TI is asking you to keep those grounds "separate" in the sense that they do not want (example) 5A of current flowing through the output switches/stages to perturb the ground reference the IC is using for it's small-signal control loop.

enter image description here

Let's say your ground plane / copper has a resistance of oh, 0.010 ohms (which is stupidly high for a copper plane). In a buck converter, let's say your bottom synchronous switch turns on and current is now flowing through the blue arrows there. With the resistance of the plane (leaving out the inductance here), Ohm's law tells us there's a 50mV drop that will occur. Nearby components that are attached to the ground plane near the path where current is flowing will have their ground perturbed by the current flow (one of the simplest things a designer can do is simply place sensitive circuitry physically separate from high-power areas).

Your part has four integrated MOSFETs -- I've illustrated below the current flow path assuming your device is in buck-mode, and the low-side switch is currently on:

enter image description here

This will perturb PGND (which in the end, is connected with as much copper as possible to your ground plane). However, the feedback amplifiers and gate drivers are going to be referenced to logic ground (the blue areas):

enter image description here

It should not be a particularly high-current path -- the largest current draw there should be the gate drivers internal to the IC. I'm going to change example diagrams here, because I think TI actually got it backwards in their block diagram view (the adjustable version should NOT have internal FB resistors):

enter image description here

That's it -- a very small current is going to flow through that path to give you your feedback voltage. In their example, as long as all of the small-signal external components (feedback divider and compensation) use only pin 7 of the controller as their return path, and you tie it to GND at one point (like under the controller like they have done), the controller will see the correct potential and 'ride the bronco' so to speak -- as the MOSFETs draw current and switch rapidly, the gate driver + controller is going to be right along for the ride.

So the weird thing to do (IMO), would be to place additional GND vias (like TI seems to have done in that layout example, between C2 and R2) on that return path, because now you've created a potential loop (red vs yellow):

enter image description here

EDIT: I figured out what that via is. It's confusing on TI's part -- it's from their development board: enter image description here

It simply is breaking out the quiet GND to test points on the EVM. So, do not put that via there -- only tie all the small signal stuff to pin 7 of the controller as they have done, following my red current return path. :)

In terms of recommended reading, I will personally say that I find Linear Tech's datasheets to have excellent layout recommendations that have served me well -- finding a similar part from them that is a four-switch buck-boost converter (like the LTC3785) should be helpful. Additionally, here is the page from Analog Devices regarding ground bounce.

Here are some thoughts on switching converter layout (in general):

  • There will always be noise. You can however manage it.
  • Keep your loop area as small as possible. That is, for the current loops that are switching large amounts of current, keep the overall loop area as tiny as possible.
  • Think of where current flows in your circuit and your product. For DC current, draw a straight line (path of least resistance) as the current flows from the battery / wall / whatever through your converter, and to the output.
  • You'll note that they have placed capacitors very, very close between VIN and GND, and VOUT and GND. This can help to minimize loop-area, and a small (0.1uF) capacitor tightly placed here can help torch high-frequency noise.
  • The SW node is a trade-off between current-capacity and noise-reduction -- keeping it as small as possible (and perhaps burying it inside the board) will help with noise reduction, but you will pay a penalty in higher DC resistance.

tl;dr -- Run all the small signal feedback components back to pin 7 on this particular controller. Do not pass GO (GND plane), do not collect $200 / ground bounce / multiple loops. Send a note to TI since I think those block diagrams are flipped.

I hope one day to have the time to sit-down and do an interactive video showing the layout of converters like this, because it actually isn't that complicated -- it really all comes down to being cognizant of where (and when) the currents flow through the circuit.

  • \$\begingroup\$ I'd love to see a video like that! In particular, it is sometimes hard to judge where the main flows are in integrated circuits with dual boost and buck paths. \$\endgroup\$ Feb 9, 2016 at 2:10

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