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I have a long and wide power trace (0.3" x 3") that is duplicated on several layers of a PCB. For some thermal purposes, there are many thermal vias punched into the trace (See Figure below). I imagine that DC resistance increases as a function of the number of vias in this trace and would like to calculate this. I'd also like to ignore actual location and placement of the vias, and am aware some simplifications may be necessary.

enter image description here

  1. Is it possible to calculate R(N_VIAS) for a single plane (with holes in it), and then parallel all planes (assuming little or no current actually goes between the planes through the vias)?
  2. Is "no current through the vias" a good assumption for DC (or low freq, e.g., 60Hz)?
  3. How do I get started deriving an analytic expression for DC resistance as a function of number of vias? No need to derive everything for me, as long as I can get a starting point.
  4. If I were to import the actual layout into a Finite Element tool, what tools are recommended for this type of analysis?

Thanks in advance for the help!

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  • \$\begingroup\$ To a first approximation, the conductance of the trace at DC is simply a matter of effective cross section. The vias reduce the effective cross section. Probably the simplest way to approximate it is by setting up a proportion. R1/R2 = A1/A2. R1 is resistance with vias. R2 is resistance without vias. A1 is area ignoring vias. A2 is A1 - via hole area. Most likely, and depending on layout details, the traces will not equally share current, because it is hard to achieve a low DC resistance connection from layer to layer. But if you manage that, then they will share pretty evenly. It is just DCR. \$\endgroup\$
    – user57037
    Commented Feb 8, 2016 at 18:25

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It shouldn't actually increase resistance noticeably. The thing to remember is the via is now part of the plane - you now have a tall cylinder of copper rather than a circle.

If you work out the area of copper you may, depending on the size of the via, find that the copper area of the via is actually larger than that of the copper that would have been in its place. Granted the via will be thinner material, but it is still unlikely to make much of a difference.

  1. In order to calculate it exactly you would need to know the dimensions of the via, the thickness of the plating, and the resistivity of the material (copper, tin, etc.) that makes up the via.

  2. Given we are talking non-RF frequencies, you can consider everything as lumped element and analysis becomes far easier. The copper plane is essentially a resistor, as are the vias. The current through the plane will distribute itself through every possible path proportionally to resistance of that path. If you have copper on both top and bottom connected through vias, and then have a supply at one end and a load at the other, the current will flow though the vias as well as the plane.

    You could if you know the resistance of the vias and the plane end up drawing out a very large and complicated tree of resistors to represent it, but in practice you will find that the numbers are so small that rounding errors during the calculations will probably be as much as the difference the vias make to the resistance.

  3. Resistance is given by the equation below (where \$\rho\$ is resistivity, \$L\$ is length, \$A\$ is area, and \$R\$ is the resistance). \$rho\$ can be found from any textbook or internet source, and the other parameters would depend on the via dimensions - unfold a cylinder into a cuboid and calculate its resistance. Calculate the resistance of the copper circle that would otherwise take its place. The second minus the first will give you the difference in resistance that the via makes to the plane.

$$R = \frac{\rho L}{A}$$

  1. No idea. Anything you want - it just involves a bit of basic integration, multiplication, etc.
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  • \$\begingroup\$ Thanks for the answer! Yes, the vias were added because they actually increased the volume of copper in the trace. However, my image above may have been misleading. Please see the new image and confirm this is what you were thinking? I believe little current will flow through the vias if DC resistance in each plane is similar. \$\endgroup\$
    – VIANDERN
    Commented Feb 8, 2016 at 18:34
  • \$\begingroup\$ @Dweeberkitty the same applies. You are not talking about RF frequencies so everything behaves like a resistor - google resistor cube as an example. \$\endgroup\$
    – Tom Carpenter
    Commented Feb 8, 2016 at 18:58
  • \$\begingroup\$ @Dweeberkitty The essence remains - you are not putting holes in. You are putting copper tubes in. Current that would be "blocked" by a "hole" can "flow" along the "sides" of the cylinder. Consider a very large tube with a tiny annulus of trace. Depending on details, no effect or a small one that could be less resistance or more. If you had board with and without the vias, a multimeter would tell the tale...and if you want to really nail the last detail (both electrically and thermally) solder copper plugs into the holes (or fill with solder, but it's less conductive than copper plugs.) \$\endgroup\$
    – Ecnerwal
    Commented Feb 8, 2016 at 19:21
  • \$\begingroup\$ It looks like connector A and connector B are through hole? And those are the only things tying together the two traces besides the vias, right? So the question is, what is the resistance between the two layers measured along the pin of connector A and connector B? If that resistance is much smaller than the via resistance, then not much current should flow in the vias. \$\endgroup\$
    – user57037
    Commented Feb 9, 2016 at 7:07

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