I have a long and wide power trace (0.3" x 3") that is duplicated on several layers of a PCB. For some thermal purposes, there are many thermal vias punched into the trace (See Figure below). I imagine that DC resistance increases as a function of the number of vias in this trace and would like to calculate this. I'd also like to ignore actual location and placement of the vias, and am aware some simplifications may be necessary.
- Is it possible to calculate R(N_VIAS) for a single plane (with holes in it), and then parallel all planes (assuming little or no current actually goes between the planes through the vias)?
- Is "no current through the vias" a good assumption for DC (or low freq, e.g., 60Hz)?
- How do I get started deriving an analytic expression for DC resistance as a function of number of vias? No need to derive everything for me, as long as I can get a starting point.
- If I were to import the actual layout into a Finite Element tool, what tools are recommended for this type of analysis?
Thanks in advance for the help!