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Given an AND gate, an OR gate, and inverters as needed, design an SR flip flop with S and R active low (0).

I understand that to make such a flip flop, I would have to place inverters on the circuit so that the AND and OR gates behave like NOR gates, as NAND with S=0, R=0 would lead to a race condition. However, I have no idea how I would place inverters in such a way for it to behave like NOR gates.

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  • \$\begingroup\$ hmmm--- why isn't there a 'homework' tag on this site? \$\endgroup\$
    – Carl Witthoft
    Feb 9, 2016 at 13:08
  • \$\begingroup\$ This question and answer may help you understand this: electronics.stackexchange.com/questions/163164/… \$\endgroup\$
    – Peter Smith
    Feb 9, 2016 at 13:09
  • \$\begingroup\$ @ImInfinite313: I told you all during class not to seek help from others on the Internet, didn't I? \$\endgroup\$
    – Alexxx
    Feb 9, 2016 at 13:57
  • \$\begingroup\$ @PeterSmith Thanks, the link explained it perfectly! \$\endgroup\$
    – ImInfinite313
    Feb 9, 2016 at 22:25
  • \$\begingroup\$ @Alexxx I'm not in your class then \$\endgroup\$
    – ImInfinite313
    Feb 9, 2016 at 22:26

1 Answer 1

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You have a bunch of questions jumbled together, and we're not going to do your homework for you anyway. However, consider this very basic flip-flop circuit:

Look at this carefully and understand how it works. You should then be able to figure things out from there.

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  • \$\begingroup\$ That looks like a latch not a flip flop. \$\endgroup\$
    – jbord39
    Aug 9, 2016 at 22:31
  • \$\begingroup\$ @jbord: The distinction is usually that a flip-flop works on the edge of the clock signal, and a latch on the level of the clock signal. This is a very basic circuit that doesn't have a clock, and can be used as the memory element of both a latch and a flip-flop. You could probably call this circuit either without really being wrong, but the latch/flip-flop distinction is neither useful nor meaningful at this basic level. That distinction is more about what you put in front of the inputs of this circuit. \$\endgroup\$
    – Olin Lathrop
    Aug 12, 2016 at 17:39
  • \$\begingroup\$ I am familiar with the differences. What you posted is a latch. You can call it a flip flop all you want, that does not make it so. And the distinction between flip flops and latches are most meaningful at the basic circuit level, which is where their nuances can be understood (different setup and hold time in a flop and latch, for example). A flip flop is two back to back latches with opposite polarity clock, creating a lock and dam system (edge triggered). Google latch based or flop based VLSI design to see the differences. \$\endgroup\$
    – jbord39
    Aug 12, 2016 at 17:46
  • \$\begingroup\$ eetimes.com/document.asp?doc_id=1278980 A link from EE times. Notice distinction between latch and flip flop. \$\endgroup\$
    – jbord39
    Aug 12, 2016 at 17:49
  • \$\begingroup\$ @Jbord: I read the latches versus flip-flop section, and it supports exactly what I said about edge versus level of the clock signal. Again, the circuit above doesn't have a clock input. \$\endgroup\$
    – Olin Lathrop
    Aug 13, 2016 at 1:12

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