# 32 Bit Increment Circuit and Verilog Program

I have to build a circuit that stores a 32-bit number. The circuit features a control signal inc that, when active, increments the stored value by 3 in each cycle. If inc is 0, the circuit simply stores its current value without modification. The input clock governs the state transitions in the circuit upon each falling edge, the input clear is used as an asynchronous reset for the stored value, the input inc is a control signal that activates the values increment and the output value is a 32-bit signal that can be used to read the stored value at any time.

I have no clue how to make a circuit diagram for this, but here's what I have for the verilog code so far:

 module increment(input clock,
input clear,
input inc,
output [31:0] value);

reg [31:0] value;

always @ (posedge clock or negedge clear)

if (clear) begin
value=32'b0;
end
else if (inc == 1) begin
value = value + 2'b11;
end
else begin
value = value;
end
endmodule


Would this make sense given the parameters? Any help on how to make a circuit out of this?

• Your mixing ANSI/non-ANSI header styles. Change output [31:0] value); reg [31:0] value; to output reg [31:0] value);. Also, assign value with non-blocking assignments (<=) – Greg Feb 9 '16 at 19:59
• This is the third homework problem you have posted, in each post in my opinion you could have 1) Spent more time analyzing the problem 2) Done more research on the web. You need to spend more time on these things, you also need to learn how to learn, some of this will take time, work and experience. If those aren't characteristics you desire then you may struggle with engineering down the road. – laptop2d Feb 9 '16 at 20:01
• I'm new to this topic and I'm mostly posting to confirm what I'm doing is correct or asking for simple tips so my grades don't suffer – dms94 Feb 9 '16 at 20:03