I have to build a circuit that stores a 32-bit number. The circuit features a control signal inc that, when active, increments the stored value by 3 in each cycle. If inc is 0, the circuit simply stores its current value without modification. The input clock governs the state transitions in the circuit upon each falling edge, the input clear is used as an asynchronous reset for the stored value, the input inc is a control signal that activates the values increment and the output value is a 32-bit signal that can be used to read the stored value at any time.
I have no clue how to make a circuit diagram for this, but here's what I have for the verilog code so far:
module increment(input clock, input clear, input inc, output [31:0] value); reg [31:0] value; always @ (posedge clock or negedge clear) if (clear) begin value=32'b0; end else if (inc == 1) begin value = value + 2'b11; end else begin value = value; end endmodule
Would this make sense given the parameters? Any help on how to make a circuit out of this?