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I have to build a circuit that stores a 32-bit number. The circuit features a control signal inc that, when active, increments the stored value by 3 in each cycle. If inc is 0, the circuit simply stores its current value without modification. The input clock governs the state transitions in the circuit upon each falling edge, the input clear is used as an asynchronous reset for the stored value, the input inc is a control signal that activates the values increment and the output value is a 32-bit signal that can be used to read the stored value at any time.

I have no clue how to make a circuit diagram for this, but here's what I have for the verilog code so far:

 module increment(input clock,
             input clear,
             input inc,
             output [31:0] value);

     reg [31:0] value;

     always @ (posedge clock or negedge clear)

     if (clear) begin
        value=32'b0;
     end
     else if (inc == 1) begin
        value = value + 2'b11;
     end
     else begin
        value = value;
     end
endmodule

Would this make sense given the parameters? Any help on how to make a circuit out of this?

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    \$\begingroup\$ Your mixing ANSI/non-ANSI header styles. Change output [31:0] value); reg [31:0] value; to output reg [31:0] value);. Also, assign value with non-blocking assignments (<=) \$\endgroup\$ – Greg Feb 9 '16 at 19:59
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    \$\begingroup\$ This is the third homework problem you have posted, in each post in my opinion you could have 1) Spent more time analyzing the problem 2) Done more research on the web. You need to spend more time on these things, you also need to learn how to learn, some of this will take time, work and experience. If those aren't characteristics you desire then you may struggle with engineering down the road. \$\endgroup\$ – laptop2d Feb 9 '16 at 20:01
  • \$\begingroup\$ I'm new to this topic and I'm mostly posting to confirm what I'm doing is correct or asking for simple tips so my grades don't suffer \$\endgroup\$ – dms94 Feb 9 '16 at 20:03
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Do you know how a d-flip flop works? 1) Go do a study on d-flip flops, make sure you know how to write code for a d-flip flop in verilog. Do a comparison for a d-flip flop and code here 2) now that you know how a flip flop works, what if you expand it to 32 bits? 3) ask yourself, what happens if I want it to store my input signal on the rising edge? on the falling edge? How do I code this up?

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  • \$\begingroup\$ so then a D flip flop would be able to do what this is asking? or would I need to combine it with other logic for it to work? \$\endgroup\$ – dms94 Feb 9 '16 at 20:00
  • \$\begingroup\$ When you use verilog (the code you posted above) is essentially 32 d flip flops in a row, but instead of storing a number, your storing the output of the flip flop plus a constant. It is essentially a counter and a flip flop. You can combine multiple logic elements in a process with a hardware descriptor language. This an important concept to learn in digital design. Another thing to think about is how this is being implemented on the FPGA. Most designs have logic elements that are switched on and off that feed into a memory element such as a flip flop. \$\endgroup\$ – laptop2d Feb 9 '16 at 20:55
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It is much easier to do this if you make the circuit first and then use a dataflow or structural implementation in Verilog based on the circuit you drew. Also, the TA emailed us this morning and said to use either a structural or dataflow model, and you are using behavioral.

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