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What is the difference between General purpose PCIe signals and PCI Express Graphics (PEG) in standard COM modules (type-6) ?

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  • \$\begingroup\$ Have you looked in the PCI spec? \$\endgroup\$ – pjc50 Feb 10 '16 at 13:48
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The difference is likely where the lanes are sourced from -- PEG sounds like Intel parlance to me. I Google searched 'COM Module Type 6 PCI Express' and it appears you're talking about the ADLink modules sold here, which are Intel based.

On most desktop x86 platforms, the PCI Express root complex is located inside the CPU itself, on-die. Since Sandy Bridge, the PCIe RC is a first-class member (so to speak) and enjoys connectivity to the high-speed interconnect on the CPU die (that also includes the DRAM controller, etc.). Generally, the PEG is implemented as a x16 link that can be (at least around Nehalem) also bifurcated into 2 x8 lanes -- new models may support additional configuration. This is generally the largest-width, fastest interconnect available.

Your average desktop computer motherboard will route the PEG lanes from the CPU to either a single x16 slot, or twin x8 slots, obviously intended for GPU applications. Industrial computers may route this link to a large PCIe switch which then breaks out into many smaller ports -- this is what products I used to work on did.

The key difference is that the PEG lanes offer the shortest possible 'hop' to the PCIe root complex. Other PCIe lanes on a platform are generally offered up by the PCH (aka southbridge), which is connected to the CPU via a DMI link. They still deliver the performance you would expect, but they are generally x1 or x2 in width as the DMI link is a bottleneck.

So, to summarize, you could design a product such that:

  • PCIe Device <--- PEG lanes ---> CPU PCIe Root Complex
  • PCIe Device <--- PCIe lanes ---> PCH <--- DMI ---> CPU PCIe Root Complex.

Without knowing more about your application, I can't comment further, but generally the PEG lanes should be used for very bandwidth-hungry devices like GPUs or a PCIe packet switch that has many downstream devices.

For Xeon-based platforms, the numbers are very different -- I believe now you can purchase a model with upwards of 40 lanes from the CPU. But for most consumer desktop platforms, I believe the current state-of-the-art is a PCIe 3.0 x16 link that motherboard vendors can choose to do what they please with.

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  • \$\begingroup\$ This answer fits (and explains for me!) the documentation of my Supermicro X11SSM-F motherboard: The motherboard diagram shows two PCI-e slots as "CPU SLOTn" (both x8) and two others as "PCH SLOTn" (both x4). Then in the BIOS it refers to the "CPU" slots (by number) as PEG and the "PCH" slots as PCI-E. \$\endgroup\$ – davidbak Nov 4 '17 at 22:43
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PEG lanes are disabled unless PEG_ENABLE# is pulled low, and they can only be used by one card on the bus, and for graphics. However, if there is an internal (integrated) GPU available, its possible to request the PEG lanes be enabled as additional general purpose PCIE lanes, however you'll get between 1x-16x of additional general purpose lanes that is entirely chipset dependent.

It's generally best practice to only use PEG lanes for graphics, as those lanes will be monopolized by a single device on the bus (making it ideal for graphics but little else).

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