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My company is building a device that is specified to have TTL outputs and I shall test them.

Reading about logic levels Wikipedia, EN (the German version has a nice table), I find the voltages of TTL and LVTTL:

TTL 5V out: low <= 0.4V , high >=2.4V

LVTTL 3.3V out: low <= 0.4V , high >=2.4V

As you can see, there is no difference in the voltages between TTL and LVTTL.

So, as far as I understand, the difference is only internal, whether our ICs operate at 5V or 3.3V and thus the maximum voltage differs, which seems not important for outputs to work properly.

Given the device was implemented with LVTTL 3.3V technology, is it fully compatible to TTL technology and should I consider the test as passed or is there anything else I should consider, e.g. current?

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    \$\begingroup\$ You might want to consider what happens if a 3.3V TTL chip receives a 5V TTL signal. \$\endgroup\$ – PlasmaHH Feb 10 '16 at 13:26
  • \$\begingroup\$ @PlasmaHH: this is about outputs only. It should not receive 5V, does it? \$\endgroup\$ – Thomas Weller Feb 10 '16 at 13:27
  • \$\begingroup\$ I don't know much of your device, but someone might wire it up the wrong way... \$\endgroup\$ – PlasmaHH Feb 10 '16 at 13:28
  • \$\begingroup\$ That's right. Given the 24V power supply is applied through the same screwed contact, it'll break anyway (sooner or later) \$\endgroup\$ – Thomas Weller Feb 10 '16 at 13:32
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TTL outputs must be able to sink 16 mA with a voltage drop of no more than 0.4 V, and to source 0.4 mA while staying above 2.4 V. (TTL inputs source 1.6 mA, so this is designed for a fanout of 10.)

LVTTL outputs, as specified in JEDEC standard No. 8C.01, must be able to sink or source 2 mA at the same voltages.

So your LVTTL output will not be able to drive more than one TTL input, unless your component is specified for a higher current.

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