I'm using the following circuit. In1 and In2 come from two separate amplifiers (Max9643), both of which are fed by a square pulse but have their inverting and non-inverting terminals criss-crossed with each other. The first stage amplifiers work well separately. Now coming to the second stage (i.e. the circuit shown below).
simulate this circuit – Schematic created using CircuitLab
When I use R1=R2=20k and R3=R4=100k, they work properly and In1 and In2 are shown below:
(This's only a spice simulation and practical output varies, especially with respect to limiting high frequency).
Now if I use R1=R2=20 and R3=R4=100, Vin2 somehow gets affected.
I realize I'm doing something wrong with the resistor values but what exactly is happening? On a practical circuit, more than voltage reduction, the edges seem to become contaminated and are jagged. I am using an op-amp with 10s of uA bias currents so the high value resistors might not be suitable for me. But if it's an input current/voltage issue why does this occur only at the inverting terminal? I've been beating myself up over this since I think this must be a basic issue, but I'm not able to put my finger on the exact cause. I'm planning to check this with a fully differential amplifier IC instead of the op-amp but I would really like to know what I'm doing wrong.