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How can I use vhdl to design a sequence detector to find a 32bit sequence with 15 zeros followed by 17 ones by using 2 counters to count ones and zeros that have enable and reset signals. Can anybody give me some clue or draw a fsm chart.

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closed as too broad by Matt Young, Sparky256, dim, Daniel Grillo, Voltage Spike Jul 28 '16 at 17:54

Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

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    \$\begingroup\$ Why two counters? You can use the same counter as long as you can 'remember' what you're counting. \$\endgroup\$ – user8352 Feb 11 '16 at 1:37
  • \$\begingroup\$ I'm wondering how to deal with the rising edge and falling edge. \$\endgroup\$ – EEEidolt Feb 11 '16 at 1:48
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    \$\begingroup\$ Why rising and falling edge? This FSM would be driven by either one to sample the input signal at fixed time intervals. \$\endgroup\$ – Martin Zabel Feb 11 '16 at 6:29
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    \$\begingroup\$ This question is backwards, you need to do the work, then ask the question about why your design doesn't work. How would it ever help you to have someone else do the design work for you? You wouldn't understand how it works. electronics.stackexchange.com/help/how-to-ask \$\endgroup\$ – Voltage Spike Jul 28 '16 at 17:54
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I'd suggest a more general approach (without counters) that needs some more gates but is much easier to understand and to debug and it can be adapted for more complex patterns.
Drawn as classical logic gates: enter image description here

The VHDL implementation is very straight forward:

  • implement a 32-bit shift register
  • check whether output vector equals reference vector

EDIT1:
If you absolutely want (have) to use counters:

  • one counter that increments with each 0 at the input.
  • another counter that increments with each 1 at the input.
  • prevent wrap-around of both counters, e.g. by disabling if they reach a count above the required value (15+1 and 17+1).
  • reset both counters if a 1 is followed by a 0 at the input
  • compare the outputs of both counts whether they show the required values

EDIT2
BTW: also the shift register solution could pass as solution using "two counters": a shift register can be seen as a unary counter. The part with the inverters is a unary counter that counts the 0s. The part without the inverters is a unary counter that counts the 1s.

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  • \$\begingroup\$ Ok, but 2 counter is one of the requirement of the question. \$\endgroup\$ – EEEidolt Feb 11 '16 at 9:22
  • \$\begingroup\$ @EEEidolt: see my 2nd edit \$\endgroup\$ – Curd Feb 11 '16 at 11:21
  • \$\begingroup\$ This is the solution I used to describe a SPI driver in a CPLD. \$\endgroup\$ – lucas92 Feb 11 '16 at 14:56

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