How can I use vhdl to design a sequence detector to find a 32bit sequence with 15 zeros followed by 17 ones by using 2 counters to count ones and zeros that have enable and reset signals. Can anybody give me some clue or draw a fsm chart.
closed as too broad by Matt Young, Sparky256, dim, Daniel Grillo, Voltage Spike Jul 28 '16 at 17:54
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I'd suggest a more general approach (without counters) that needs some more gates but is much easier to understand and to debug and it can be adapted for more complex patterns.
Drawn as classical logic gates:
The VHDL implementation is very straight forward:
- implement a 32-bit shift register
- check whether output vector equals reference vector
If you absolutely want (have) to use counters:
- one counter that increments with each 0 at the input.
- another counter that increments with each 1 at the input.
- prevent wrap-around of both counters, e.g. by disabling if they reach a count above the required value (15+1 and 17+1).
- reset both counters if a 1 is followed by a 0 at the input
- compare the outputs of both counts whether they show the required values
BTW: also the shift register solution could pass as solution using "two counters": a shift register can be seen as a unary counter. The part with the inverters is a unary counter that counts the 0s. The part without the inverters is a unary counter that counts the 1s.