I need to take one sample of a fast changing signal at exact time with high precision. Slow sample rate ADC's have better accuracy, but I wonder about actual aquisition time - the time at which ADC is doing sample and hold. I guess it effectively averages the signal between some points in time. Can a slow (say 10 ksps) ADC take a fast snapshot, say less than 1us? Or is it always related to samples per second? 1 msps ADC obviously does sample and hold in less than 1us, but how about 100ksps, 10ksps ADC? After looking at some datasheets, I'm still confused.
The parameter I think you want is in the datasheet of high performance ADCs - it's called "Input Bandwidth". You may want to also consider the "Aperture Delay" and the "Aperture Jitter" which define how closely, and how consistently the sample is done relative to the clock edge. Aperture jitter effectively adds noise.
It becomes very important when you are doing undersampling. If you are interested in a relatively narrow bandwidth in a relatively high frequency signal you can undersample and bandpass filter- say you have a 100MHz signal and are interested in 50kHz bandwidth- you can sample the 100MHz signal at 100kHz and Nyquist is still satisfied. Of course you'd want to bandpass filter the signal before doing this. You cannot do it if the samples are smeared out over time so the input bandwidth has to be better than 100MHz for it to work well.
Here is another example, this one from a 50 ksps to 200 ksps SAR converter:
Here they refer to the full power bandwidth. Note that an inexpensive converter that can handle at most a 100kHz bandwidth without aliasing has a full-power bandwidth of as much as 11MHz.
Delta-sigma converters (the other most common type) behave quite differently- very long latency and group delay. They are effectively oversampling converters followed by filters.
Slow or not, successive approximation A/Ds like what you seem to be talking about have a sample and hold in front of the actual converter. That freezes the signal almost instantaneously.
The real question therefore is what kind of low pass filtering is in front of the sample and hold. The more LPF, the longer the time window over which the held value is a blend of. Actually, this time window extends backwards to infinity, but the importance of values falls off with age such that at some point you can ignore them because they are below your noise floor, or at least 1/2 LSB or so.
You can control some of this low pass filtering, but some is always there you can't do anything about. The sample and hold is usually implemented as a capacitor with a FET in series. During sampling, the FET is on, and during the hold time it is off. Various resistances add up so that the effective resistance of this switch when on can be significant. That resistance together with the sample and hold cap form a R-C low pass filter you're stuck with.
I just looked up values for a microcontroller A/D that can do 12 bits at 1.1 Msamp/s. The total series resistance from the pin to the hold cap is about 3 kΩ, and the hold cap is about 4.5 pF. That comes out to a time constant of 13.5 ns. At 12 bits, it takes 7.3 time constants to decay to 1 LSB. The time window of relevant signal prior to the hold is therefore 112 ns.
Dedicated A/Ds probably have lower on resistance to the external signal during sampling, which would decrease this time. Slower A/Ds probably have a longer time because a larger resistance or larger hold capacitance could be afforded in favor of other parameters.
The impedance of your signal driving the A/D pin adds to the resistance and lengthens the effective sample window. For the fastest operation, you have to buffer your signal at a low impedance.
If you need the utmost in instantaneous sampling and don't care so much about conversion time, you can add your own sample and hold to the input of the A/D.