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I wonder if there is a difference between creating several instantiation of a single module and to instantiate different modules (with identical hardware code) only one time.

For example, I want to make an operation --binary division--, I need to do 2 divisions consecutive, example B = 1 / A and C = A / 28, which I need to happen at the same time, so I create the module in another file named Bin_Div. In the top module I type

 Module top_mod_oper (A,B,C);
 input [31:0] A; 
 output [31:0] B, C;


 Bin_Div inst1 (

 .dataa (A),
 .output (B));


 Bin_Div inst2 (

 .dataa (A),
 .output (C));

 endmodule

that will create 2 independient hardware, correct? would it be the same that just create a second Bin_Div, for example

   .
   .
   .
 First_Bin_Div inst1 (

 .dataa (A),
 .output (B));


 Second_Bin_Div inst1 (

 .dataa (A),
 .output (C));

 endmodule

And Another question, what should I do if I want them to happen consecutively, it means one after the other using the same hardware Bin_DiV.

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    \$\begingroup\$ You should end up with the same hardware in both cases. The only difference will be minor (how they are named). You can easily prove this to yourself by synthesizing both, and looking at the resulting code. \$\endgroup\$ – toolic Feb 13 '16 at 14:01
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In the first case, one of the modules will get 'optimized away' as the outputs are equivalent and can simply be connected together (same module, same inputs, same parameters, so outputs will be the same). In the second case, this will also happen if the module contents are identical. If the module contents are different or if the inputs/parameters are different, then the result will be two different sets of logic (well, it could be optimized such that some parts are shared, but the outputs should be distinct).

If you want things to happen sequentially, then I think you will have to put them in the same module and use a state machine or similar to sequence the operations. If they are in two separate modules, then you could use enable signals of some sort and sequence that externally, but you might not get any area savings from logic that could be re-used for the sequential operations.

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If you need two binary dividers running at the same time, then you need two binary divider circuits. Whether you write the divider twice or put it in a module and instantiate it twice, the effect is the same.

If you want to have one binary divider and share it, then you need some way to arbitrate access. Lots of ways to do this.

One way would be to have two inputs, each with a separate "request" signal, one output, and two "done" signals. Each of the two components that wants to share the divider puts a value on one of the inputs and raises the corresponding "request" signal, then reads the result when its "done" goes high.

Or, if you know the components using the divider will never conflict, you could come up with some scheme whereby the components would always put 0 on the their inputs when they don't need the divider. Then you could OR the inputs together and divide that. You could arrange this if, for example, you were running a continuous process that required 10 clocks and one component only needed the divider on clock 3 and the other only needed it on clock 6.

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