I'm trying to implement a simple 9-bit frequency divider using the LPM_counter Module. Hardware and Software being used:
- ALtera Max V-CPLD
- Quartus II 64 bit Web Edition 15.0
- ModelSim Altera Starter Edition 10.3d
I wrote a program in Block schematic format (BDF) adn downloaded it into the cpld and it works fine, giving the desired output. However when I try to simulate it in ModelSim it gives 'z' (high impedance) on all outputs.
For the simulation I created a Verilog file from the BDF file using the 'Create HDL design file fron current file' option in Quartus. Then I wrote A testbench to simulate a clock input for the LPM_counter module.
I've tried a lot of different things that I've read from different forums such as trying to run it without a testbench by giving a Clock input directly in ModelSim, trying reg outputs instead of wires and vice versa, amongst other things.
I've been stuck on this for a while now and really need it to work because I'll be needing ModelSim to make programs for some upcoming projects. I'm doing this to get used to the whole process before I actually work on it.
Btw I made a frequency divider using JK flipflops and that worked fine on both, the cpld and ModelSim simulation. Its just this black box module that I'm having problems with.
Source File (Converted to Verilog from .bdf)
module ninebitlpm( myclk, q ); input wire myclk; output wire [8:7] q; // only using the two most significant bits wire [8:0] q_ALTERA_SYNTHESIZED; lpm_counter b2v_inst( .clock(myclk), .q(q_ALTERA_SYNTHESIZED)); assign q[8:7] = q_ALTERA_SYNTHESIZED[8:7]; endmodule module lpm_counter(clock,q); /*synthesis black_box */ input clock; output [8:0] q; endmodule
`timescale 1us/1ns module test_lpm(); reg myclk; wire [1:0]q; ninebitlpm mycounter(myclk, q); initial begin myclk = 1; forever #1 myclk = ~myclk; end endmodule