I wrote a verilog code for a 4 by 9 bit register:
module reg_file(input rst,
input clk,
input wr_en,
input rd_en,
input [1:0]rd0_addr,
input [1:0]rd1_addr,
input [1:0]wr_addr,
input [8:0]wr_data,
output reg [8:0]rd0_data,
output reg [8:0]rd1_data);
reg [8:0]mem[3:0];
integer i;
always @(posedge rst or negedge clk)
begin
if (rst) begin
for (i=0; i<4; i=i+1)
mem[i]=0;
end
else if (wr_en) begin
mem[wr_addr]=wr_data;
end
else (rd_en) begin
assign rd0_data = mem[rd0_addr];
assign rd1_data = mem[rd1_addr];
end
end
endmodule
but using iverilog to check if there are any issues, it says:
26: syntax error
27: Syntax in assignment statement l-value.
30: syntax error
I can't seem to figure out why I'm getting these errors, can anyone help?
I also need to find test vectors to test every possible outcome of the register file, does anyone have any suggestions on the best way to do that?