I designed a circuit to read analog signal, in range of -10V to +10V with resolution of 1mV. I need to validate my design by testing it in different input voltages. So I soldered a voltage divider circuit using a potentiometer. But I think it is not a good way due to the fact that it affects actual voltage by drawing current. Other way is to use an op-amp as a voltage buffer to eliminate effect of voltage divider circuit. I want to know: how to make a circuit to provide different input voltages for ADC with negligible effect on ADC? Thanks in advance.
EDIT1: Link suggested by Roger Rowland is about validating procedure, but my question is about the circuit which provides different input voltages for ADC with negligible effect.
EDIT2: I measure the voltage test by Fluk8846A. When I connect it, voltage changes and oscillates 4mV peak to peak. How Can I remove the noise induced by Fluk?