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I want to design a full adder of one bit numbers using 2/4 Decoders and NOR gates.

I have the truth table: enter image description here

Now, what's confusing me are the inputs and outputs. The inputs for one DEC would be A and B, right? What do I do with Cin and Cout? Everything goes into the NOR gate and there's S, but how to get there?

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  • \$\begingroup\$ Just build some 3:8 decoder out of multiple 2:4 decoders \$\endgroup\$
    – PlasmaHH
    Commented Feb 18, 2016 at 12:21
  • \$\begingroup\$ Then I would use 2 decoders, the inputs would be A and B and control input Cin... The rest is just like 3/8 decoder, with numbers 0 to 7 going into the gates and making S and Cout. Is this correct? \$\endgroup\$
    – Quant
    Commented Feb 18, 2016 at 12:30
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    \$\begingroup\$ Do you understand how two half-adders can be combined to make a full adder? \$\endgroup\$
    – Dave Tweed
    Commented Feb 18, 2016 at 12:58
  • \$\begingroup\$ @DaveTweed No, not really. \$\endgroup\$
    – Quant
    Commented Feb 18, 2016 at 15:15
  • \$\begingroup\$ See my answer below. U1 and NOR1 constitute a half-adder, and so do U2 and NOR2 (albeit with a slight twist). Note that I'm assuming that this is a homework problem, which is why I'm not giving a complete answer here. If you want more explicit help, you're going to have to be more clear about where this problem came from and what you DO understand about it -- and what you understand about logic design in general. \$\endgroup\$
    – Dave Tweed
    Commented Feb 18, 2016 at 15:21

2 Answers 2

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If you are constrained to use decoders and NOR gates, the logic is a whole lot simpler if you redefine the carry inputs and outputs to be active-low instead of active-high. I'll present a solution based on this, and maybe it will provide some insight to your original problem.

schematic

simulate this circuit – Schematic created using CircuitLab

Actually, it only requires one additional gate to make them active-high, but I'll leave that as an exercise for the reader.

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enter image description here

Full adder using 2 to 4 decoders.

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  • \$\begingroup\$ Hi @Ashok, welcome to EE.SE. Can you please explain how is this answer different from the previous answer by @DaveTweed? \$\endgroup\$
    – Hazem
    Commented Sep 7, 2018 at 5:31

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