# VHDL: Is it possible to have a “variable length” string in VHDL like in programming languages?

According to the package named Standard in VHDL, the string is actually declared as array of character type where the character type itself is also defined within the package.

Provided that I am filling in a string with data which shall then be written to a file and the size of the string cannot be known in advance, how do I declare a "variable length string"?

I am aware that the Line type exists from textio. However, I don't know if it is possible to actually concatenate different line variables and then write them to a file. If this is possible then my problem can be solved.

• Using NUL as a fill character is not supported by all VHDL tools. Using characters greater then CHARACTER'val(127) in source code is not allowed (VHDL files are ASCII encoded not ANSI) and explicitly using CHARACTER'val(255) causes some VHDL tools to crash or to write the synthesis log window in reverse order .... Have a look at our PoC.strings package on how to implement several string functions for fixed sized strings. – Paebbels Feb 19 '16 at 2:53