Lets say we have two process statements in VHDL both reacting on the same clock edge.
Beside the clock we also have for example the reset signal. I know that only one process can modify the reset signal otherwise we get multiple drivers error.
Now lets assume one of the processes is modifying the signal and the other one is reading it. Which will evaluate first. Or in otherwords will the signal change be triggered in both processes and the code will work as expected ?
To clarify here is the VHDL code.
-- First process process (clk, reset) begin if rising_edge(clk) and reset= '1' then -- do work end if; end process; -- Second process process (clk) begin if rising_edge(clk) then case reset is when '1' => reset <= '0'; when '0' => reset <= '1'; end case; end if; end process;
The code is hypotetical and totaly irrelevant. But will the first process execute on every other clock or not.
Based on a test this will happen. But can I assume this will always happen or not.
Thanks in advance.