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I am trying to make a circuit which would measure the time interval between two pulses accurately. For this I have decided to use an OCXO with CMOS output and the LPC1114FN28 microprocessor.

I plan to drive the micorprocessor using the OCXO output to the XTALIN pin and the pulses whose interval is to be measured is fed into the CT32B0_CAP0 pin, the 32 bit timer operates in "capture" mode, wherin the number of PCLK clock cycles between the rising edges of the pulses gets transferred from the TC register to the capture register.

My doubts:

(1) Will using a CMOS OCXO output connected to the XTALIN pin drive the uC? What should I do with the XTALOUT pin?

(2) If I use the internal PLL to increase the frequency, will the accuracy of the PCLK clock be degraded as compared to the OCXO output?

Any ideas? Abhishek

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  • \$\begingroup\$ There is guidance in the datasheet on how to use an external oscillator in section 12.3 cache.nxp.com/documents/data_sheet/LPC111X.pdf?pspll=1 \$\endgroup\$ – Peter Smith Feb 20 '16 at 15:29
  • \$\begingroup\$ Hello Peter, Yes I have seen that, but it deals with using crystals with capacitors. I am talking of a crystal oscillator "package", which has only Vcc, Ground and Osc. Out pins. \$\endgroup\$ – Abhishek Feb 20 '16 at 15:34
  • \$\begingroup\$ Abhishek: the section involved states "If the oscillator is driven by a clock in slave mode..." - a clock is how we often refer to an external oscillator, which is what you have. So use the guidance here for driving xtal in from your oscillator. \$\endgroup\$ – Peter Smith Feb 20 '16 at 15:37
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According to Page 97 of the Datasheet:

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg).

In slave mode, a minimum of 200 mV (RMS) is needed. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 49), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected.

This basically answers your question (1). You can use an external clock to drive the XTALIN pin as long as you limit the voltage swing to between 200mV and 1000mV RMS. The (NXP) recommend doing this using two capacitors to AC couple the clock and act as an attenuator. See the diagram on page 97.

It also goes on to say you should leave XTALOUT unconnected - i.e. don't connect anything to it, not ground, not a resistor, nothing.


As for question (2), the job of a PLL is to produce a clock which is at a higher (or lower) frequency to the reference clock, but one which is phase locked to it. In other words if you were to have a x2 PLL, you would have an output clock of exactly 2x the input clock assuming the PLL has locked.

It is possible you will get some drift in the clock, but this will be limited by the PLL as to how far it goes before being corrected. The maximum drift determines how much jitter you get on the clock - something which should be specified in the datasheet somewhere (haven't looked) doesn't appear to be specified in the datasheet though. The jitter is basically a small variation of frequency as the rising and falling edges of the clock are not at exactly the right moment due to the PLL bandwidth and drift correction.

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  • \$\begingroup\$ So it appears using a CMOS output oscillator is out of question. The one that I am planning to use has a minimum HIGH voltage of 4.5 V and maximum LOW voltage of 0.5 V, so the swing is 4 Volts. \$\endgroup\$ – Abhishek Feb 20 '16 at 16:16
  • \$\begingroup\$ Further, using the PLL loop will introduce drift and hence errors into the interval measurement \$\endgroup\$ – Abhishek Feb 20 '16 at 16:19
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    \$\begingroup\$ @Abhishek 4.5V is not an issue, that's what the capacitors described on page 97 are for. Doing the calculation \$C_g = \frac{V_o C_i}{V_i-V_o}\$ gives about 30pF for Cg when using the recommended Ci (100pF). As for the PLL drift, this should only happen if the PLL is not locked. Once it is locked all you will see is jitter - you should never see drift more than half a clock cycle either way. \$\endgroup\$ – Tom Carpenter Feb 20 '16 at 16:23
  • \$\begingroup\$ Thanks for clearing up the first point! Regarding the other one, I am planning to use AOCJY1-A-10MHz OCXO, which is available rather cheap at element-14. The stability for this device is mentioned as 50 ppb. You mentioned that the drift using the PLL is half a clock cycle, either way, or in other words 0.5 Hz/ 10 MHz = 50 ppb. So using the PLL will increase the total error to 100 ppb. Of course, I could leave out the PLL altogether and live with lower clock cycles. \$\endgroup\$ – Abhishek Feb 20 '16 at 16:33
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    \$\begingroup\$ The other option I am thinking about, is to use the inbuilt oscillator (12 MHz) and PLL to make the PCLK 48 MHz, but send the OCXO output to the CT32B0_CAP0 pin with the 32 bit timer/counter configured as a counter. The pulses whose interval I need to measure trigger an interupt in any of the GPIO pins during which I copy and reset the content of the TC register. \$\endgroup\$ – Abhishek Feb 20 '16 at 16:38

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