When is using latches better than flip-flops in an FPGA that supports both?
It is a well-known principle that level-sensitive transparent latches should be avoided in FPGAs, and edge-sensitive flip-flops should be used exclusively. Most FPGA architectures natively support both latches and flip-flops.
The general advice -- even from the FPGA vendors -- is to watch out for latches, or never use latches, etc. There are very good reasons for this advice, the details of which is all well-known. However, most advice is phrased, "don't use latches unless you know you need them".
I am an experienced FPGA designer, and over the years every time I thought I knew that I needed a latch, a quickly realized that there was a better way to do it with flip-flops. I am interested in hearing examples of when using latches is unequivocally better.
Latches vs. flip-flops often gets people riled up. I am only interested in the answer to the question. Responses explaining the difference between latches and flip-flops, expounding reasons to use NOT use latches, detailing why flip-flops are better than latches, talking about how latches are better in non-FPGA targets, etc, would be totally off-topic.