I've not looked at the 8080 in particular, but a common factor was that if all MOSFETs on a chip are made with the same process parameters, the amount of current that will flow through one will be a function of the difference between the voltage on the gate and the more higher (for PMOS) or lower (for NMOS) of the other terminals. A PMOS chip wold use switching transistors to drive signals high and passive pull-downs to drive them low; NMOS would do the opposite.
If an NMOS chip were to use a resistor for its passive pull-up circuits, they would pass through a lot more current when the connected output was being driven low when it wasn't, even though that would also be the time when one would want to minimize the current through them. Using a transistor with a fixed gate voltage may be better, but the pass-through current will fall off substantially as the output voltage gets within about 2 volts of the gate voltage. Using a gate which is biased to a high voltage like +12 would mean that Vgs would be 12 volts when the output is at ground and 9 volts when it's at +3, meaning that a pull-up sized to present an acceptable amount of output current at +3 volts wouldn't supply outrageously much when the output was at ground. By contrast, if the gate supply were +5 volts, the output current would fall off enormously as the voltage approached 3 volts (at 2.5 volts, it might supply less than a quarter the current it was supplying at ground).
As for the negative supply, I'm not positive, but I suspect the motivation was to ensure that the chip wouldn't have any difficulty pulling outputs all the way to ground. TTL standard require that a "low" output be very close to ground, and chips like the 8080 were designed to interface with such things. I don't know what motivated the use of -5 rather than e.g. -2, but perhaps someone else can chime in. It may be that having a total of 17 volts of headroom to play with would allow some kinds of pass-gate logic which would otherwise not be practical.