Also, which part of an integrated circuit has been affected by Moore's law most?

Is it the memory (caches, embedded memory, etc.)?

Or is it the logic (execution units, control units, etc.)?

Or something else?

Ideally with numbers/percentages.

  • 4
    \$\begingroup\$ Moore's law is fundamentally an economic law, and it has been given so many interpretations over the years that it is not really clear in what sense it holds today. Memory is denser than logic, but that's not necessarily meaningful in terms of economics. It depends on the available markets, etc., which have changed radically since the mid-60s. \$\endgroup\$ Feb 23, 2016 at 9:18

3 Answers 3


Pretty much everything.

One thing slightly less affected by Moore's Law, as you put it, is some, but very far from all, aspects of power electronics. But even there, finer projection systems, more accurate etching, higher quality vision systems, they all still make a difference in the qualities and capabilities of the devices.

Moore's Law simply predicted the self-driving cycle of higher accuracy processes, that enable the construction of better machines, which then drive more accurate production.

And as is to be expected on a single chip people don't design something for a 22nm process and then also something for a 340nm process, since the latter would be wasting "high cost real-estate space", whereas it could be smaller when designed for 22nm as well, which means more total devices on the same wafer, which means by comparison cheaper Chips.

There's two more exceptions (that I can readily think of) to the rule, which states that the number of transistors on a given square of silicon will grow at a steady exponential rate for several decades (which have already passed, and true to prediction we now talk more about processing power than number of transistors, as it has become all a bit fuddled in modern processing systems). I'm afraid both exceptions don't concern transistors or processing power, so they pretty much fall outside the law.

The first other exception is on-chip capacitances and resistances. They still shrink, as the barrier layers can become smaller with higher accuracy processing, but to the best of my knowledge they do not shrink at the same rate as the transistors do. They may have even already nearly stopped, because we're getting too close to Quantum Effects in the layer sizes we could make inside pure capacitances anyway.

Another exception to a certain degree are MEMS (Micro Electro-Mechanical Systems) and LEDs (Light Emitting Diodes - I know you know, but if I write out MEMS, you know....), these do use "15 to 30 year old" technology. Sometimes literally when it comes to the LEDs on your cheap Chinese LED string with sub-par colour matching and brightness. But even there Moore's Law has driven the developments of the last years, as more experience develops and more readily available machines with 100nm to 1μm feature size capability cycle on a second hand market, allowing easier and cheaper experimentation and trial and error.

  • \$\begingroup\$ Thanks for the additional details. Could you please also add a paragraph or so elaborating on the densest part ("as of now", so to speak) of ICs? I mostly wanted to know about the density we have today. Although I'm not an electrical engineer, but it seems to me we can talk about density per se, how it evolved and where we are now, and so on. \$\endgroup\$ Feb 23, 2016 at 12:41
  • 2
    \$\begingroup\$ @LeoHeinsaar I interpret the first sentence of this answer, "Pretty much everything" to mean that the density of most ICs is pretty much uniform across the bulk of the IC. And then I interpret the first full paragraph to mean, "maybe the power electronics on the IC are a little less dense than the rest". So there is no densest part. \$\endgroup\$ Feb 23, 2016 at 14:13
  • 2
    \$\begingroup\$ SRAM tends to be the densest in terms of transistors per unit area both because of routing/layout/drive strength issues and the justifiable design effort for density (for last level caches). I think SRAM tends to track the ideal density closer than "random logic", but I suspect that this is a relatively minor factor (i.e., the density factor not being much greater in 90nm than 22nm). \$\endgroup\$
    – user15426
    Feb 23, 2016 at 14:47
  • \$\begingroup\$ @ToddWilcox Pretty Much Everything was more aimed at the body of the question, to be honest at reading "Moore's Law" the whole title already started to shift out of my mental FIFO. Mr Clayton is of course right that Memory-based designs such as SRAM and/or FPGA are in any given feature size most likely to be the most dense, while there are always exceptions to any rule. Which one in which feature size is most dense perse I can only leave to others, as I know loads more about the processing and technology (I-Line-grade through EUV-grade) than actual modern Chip design. \$\endgroup\$
    – Asmyldof
    Feb 23, 2016 at 15:29
  • \$\begingroup\$ @PaulA.Clayton 's comment actually gives the closest answer to what I was looking for. But many thanks also to all the other useful comments and answers. I too have viewed "Moore's law" as something of a pseudo-law - something folks have observed, formulated (by Moore, of course) and then decided that we now have to follow it, because if we don't, Intel stock goes down and the apocalypse nears. I just used the term as a shorthand reference - to understand current state of density and which IC parts were affected over the years most. \$\endgroup\$ Feb 24, 2016 at 6:30

Here, Wikipedia what says about a transistor number count on an integrated circuit. Today FPGA are the most complex integrated circuits with more than 20 billion transistors (combination of memory and logic function). Processors reach ten billion transistors.
Every island inside of FPGA contains many logic functions, the Table of logic functions give the transistor count of each logic function.
The random acces memory DRAM, SRAM considered as the roadblock of the moore's law.
However moore's law is not the best way to comparing the chips performance. Having more transistors doesn't mean better performances.

  • 1
    \$\begingroup\$ I didn't mean to consider performance at all. I was just concerned about the density. Good point about FPGAs though. \$\endgroup\$ Feb 23, 2016 at 11:32
  • 1
    \$\begingroup\$ Excellent addition concerning the titular matter I forgot about. I'll give you a +1 and leave out of it, as it's not my knowledge. I'm not much of a modern (post 2000) Chip Designer, much more experienced with the processing and tech behind it :-) \$\endgroup\$
    – Asmyldof
    Feb 23, 2016 at 15:32

Have a look at the roadmap: International Technology Roadmap for Semiconductors.

Process scaling affects all the digital logic to the same extent. It is almost possible to just do a complete die shrink when going from, say 32nm to 22nm, leaving everything in the same place just smaller. (It does require a small amount of re-tuning, but much less work than from scratch). This is the "tick" of Intel tick-tock.

However, given the reduced die size, there is then the option to make it larger again by adding more of something. Maybe more execution units, maybe more cache, maybe a more sophisticated branch predictor. That is the "tock".

(DRAM is produced by a slightly different process using very similar tools, so it also scales at roughly the same rate).


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.