What does edge triggered and level triggered mean?

Question

I am studying 8085 microprocessor architecture and the terms edge triggered and level triggered confusing me really very much. Can anyone explain me it in layman's words ?

While studying the interrupts of 8085 named RST 7.5, RST 6.5, RST 5.5 and TRAP i came across these terms and they confused me. Here i have attached one document link from which i was reading and i have mentioned my confusion diagrams.

in the document

RST 7.5 -> Edge triggered
RST 5.5 -> Level triggered.
TRAP    -> Edge triggered and Level triggered.
           (why does it make any difference?).

the document link

Answer 1

I didn't read you document really, but I can understand why you are confused. But it is a very simple concept really. Let me explain.

Triggering: This means making a circuit active. Making a circuit active means allowing the circuit to take input and give output. Like for example supposed we have a flip-flop. When the circuit is not triggered, even if you give some input data, it will not change the data stored inside the flip-flop nor will it change the output Q or Q'. Now there are basically two types of triggering. The triggering is given in form of a clock pulse or gating signal. Depending upon the type of triggering mechanism used, the circuit will become active at specific states of the clock pulse.

1. Level Triggering: In level triggering the circuit will become active when the gating or clock pulse is on a particular level. This level is decided by the designer. We can have a negative level triggering in which the circuit is active when the clock signal is low or a positive level triggering in which the circuit is active when the clock signal is high.

2. Edge Triggering: In edge triggering the circuit becomes active at negative or positive edge of the clock signal. For example if the circuit is positive edge triggered, it will take input at exactly the time in which the clock signal goes from low to high. Similarly input is taken at exactly the time in which the clock signal goes from high to low in negative edge triggering. But keep in mind after the the input, it can be processed in all the time till the next input is taken.

That is the general description of the triggering mechanisms and those also apply to the 8085 interrupts.

Answer 2

On an 8085, TRAP is a non-maskable interrupt normally used to handle errors such as a power failure.

If it were level triggered, its code could never execute because it's an unmaskable interrupt. The handler would start executing when it became active, but it would still be active, so the handler would start executing, but it would still be active, so the handler would start executing, etc., etc. Therefore it has to be edge triggered.

However, edge triggering is a problem when the line may have glitches. Glitches may cause the handler to be invoked multiple time as the line glitches. It's a very big problem with TRAP since it is non-maskable and results in a RST.

As a compromise, the TRAP works as if it is level triggered, except that it is only recognized when it has been low since the last time it was recognized. That ensures that the TRAP handler is only invoked once.

This is what they mean by "edge triggered and level triggered".

Answer 3

*Triggering* means making a circuit active. In level triggering the circuit will become active when the gating or clock pulse is on a particular level. In edge triggering the circuit becomes active at negative or positive edge of the clock signal.

Answer 4

Golaž and vsz state it well:

Its exactlly what is says.

If edge interrupt is set, the ISR will only get fired on falling/rising edge of a pulse. While if level sensitive interrupt (as you say) is set the ISR will get fired everytime there is a low-level/high-level signal on the corresponding pin.

In short, edge interrupt gets fired only on changing edges, while level interrupts gets fired as long as the pulse is low or high.

So if you have low-level interrupt set, MCU will keep executing the ISR as long as the pin is low.

That is, it will leave and re-enter the ISR again and again, as long as the pin is low.

My impression is that no one has really answered what it means to be both level- and edge- triggered. And I haven't, either.

D Krueger's answer correctly explains what it means to be both level- and edge- triggered. (At least, his answer sounds correct to me, even though I'm not familiar with the 8085.) Golaz and vsz's answer assumes that the interrupt is masked. I'm still not sure how "except that it is only recognized when it has been low since the last time it was recognized." differs from being edge-triggered, however.