What is the difference between a latch and a flip-flop?

What I am thinking is that a latch is equivalent to a flip-flop since it is used to store bits and is also equivalent to a register which is also used to store data. But after reading some articles on the internet I found differences between latches and flip-flops based on edge triggered and level sensitive functionality?

What does that mean? Is a flip-flop the same as a latch or not?


9 Answers 9


A flip flop is built from two back to back latches with opposite polarity clocks, which form a master slave topology.

The type of latch is irrelevant (JK, SR, D, T) to this constraint, but it is important that the transparency is controlled by some pin (call it clock or enable or whatever you like).

SR latches throw everyone for a loop because the most basic design is transparent all the time. So, once the clock enable is added people start calling it a flip flop. Well, it isn't; it is a gated latch. You can build a SR flip flop out of two gated SR latches however:

true SR flip flop

Or two JK latches:

true jk ff

Or two D latches: enter image description here

Adding a clock pin to a latch (SR or JK) does not make it a flip flop -- it makes it a gated latch. Pulsing the clock to a gated latch does not make it a flip flop either; it makes it a pulse latch (pulse latch description).

Flip flops are edge triggered and the setup and hold times are both relative to this active edge. A traditional flip flop will not allow any time borrowing through cycle borders, since the master-slave topology acts like a lock-and-dam system to create a hard edge at the active clock.

Latches on the other hand setup to the transparency of the latch and hold until the latch closes. They also allow time borrowing through the entire transparency phase. This means that if one half cycle path is slow and the other half cycle path is fast; with a latch based design the slow path can borrow time into the fast paths cycle.

A very common design trick when you need to squeeze every picosecond out of a path is to spread the flip flop apart (into two seperate latches) and do logic in between.

Basically the setup and hold times are completely different between a latch and a flip flop; in terms of how the cycle boundaries are handled. The distinction is important if you do any latch based design. A lot of people (even on this site) will mix the two up. But once you start timing through them the difference becomes crystal clear.

Also see:

good text describing latches and flip flops

What is a flip flop?


Just showing a t-gate based D-flip flop (notice it is built from two back to back t-gate based D latches with opposite phase clocks).

t-gate based d ff

  • \$\begingroup\$ Hi jb going for the old revival badge? In my books a "latch" is an asynchronous memory register while a "flip flop" is a synchronous memory register , some with async features called Set/Reset. By de facto, all synchronous operations are edge sensitive. \$\endgroup\$ Nov 17, 2016 at 21:10
  • \$\begingroup\$ @TonyStewart.EEsince'75: Heh, Someone else answered right before me. Yes I am familiar with that definition but it is a bit handwavey. I think it is much clearer to realize that flip-flop is built from two latches with opposite phase clocks. This gives a very accurate picture of exactly what is happening inside and a greater understanding of the setup and hold times. It is an important distinction when characterizing standard cells or doing any custom data path design. It also leaves room for ambiguity:time borrowing flip flops,for example,have an asynchronous character around active clk edge. \$\endgroup\$
    – jbord39
    Nov 17, 2016 at 21:30
  • \$\begingroup\$ Replacing flops with pairs of latches that operate on different clock phases introduces the possibility of including dead time between those phases. If some chips activate their front-end latches only when their clock input is below (1/3)VDD, and the back-end latches only when the clock input is above (2/3)VDD, chips that share the same clock will be able to communicate reliably even if they don't see the clock switch at the exact same moment, provided that all chips have seen the clock rise above (1/3)VDD before any see it above (2/3)VDD. Such a design would seem to be... \$\endgroup\$
    – supercat
    Nov 17, 2016 at 21:50
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    \$\begingroup\$ +1. This is the best answer, IMO. The other ones, in a way or another, muddle the difference between edge-triggering (FF) and gating (gated latches). A bit heavy on the implementation side, especially for beginners. A nitpick: you seem to imply that the only technique for implementing edge triggering is coupling two latches in a master-slave configuration. I'm not an expert, but I think (IIRC) there are other tricks to implement edge-triggering. \$\endgroup\$ Jan 23, 2017 at 10:46
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    \$\begingroup\$ @mrbean: i think you are quoting a singular source that you don't really understand. Most of what I said is in-line with this "electronics handbook", which I have never and will never read. I have worked for 3 years as a CPU library designer providing latches, flip flops, register files, and other memory elements and 2-3 years as a custom circuit designer using these memory elements. Everyone has a slightly different definition of what these things are. However, designing/tuning/characterizing them for setup/hold/delay will illuminate the differences. \$\endgroup\$
    – jbord39
    Apr 12, 2019 at 15:00

The basic difference is a gating or clocking mechanism. For example, let us talk about SR latch and SR flip-flops.

An SR Latch will look like this

SR Latch using NAND gates

In this circuit when you Set S as active the output Q would be high and Q' will be low. This is irrespective of anything else. (This is an active low circuit so active here means low, but for an active high circuit active would mean high)

An SR Flip-Flop (also called gated or clocked SR latch) looks like this.

enter image description here

In this circuit the output is changed (i.e. the stored data is changed) only when you give a active clock signal. Otherwise, even if the S or R is active the data will not change. This mechanism is used to synchronize circuits and registers so that the data does not change unnecessarily.

  • \$\begingroup\$ so can i conclude that latches are level triggered and flip flops are edge triggered? \$\endgroup\$ Nov 7, 2011 at 6:59
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    \$\begingroup\$ Latches are not triggered at all. As soon as I give input, I get the output in latches. Flipflops are triggered as in I have to give a clock trigger to convert my input into output. \$\endgroup\$
    – Rick_2047
    Nov 7, 2011 at 7:16
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    \$\begingroup\$ That is not a SR flip flop. That is a gated SR latch. The setup and hold times of this circuit will function just like any other latch with an "enable transparency" pin. A flip flop is a master-slave configuration. Just think about going from cycle to cycle with this latch. You cannot. You would need two latches with opposite phase clocks (hence a flip flop) \$\endgroup\$
    – jbord39
    Nov 17, 2016 at 20:59

A latch passes the input data thru directly in the open state, and freezes the output in the latched state. The latch responds to the level of the control signal.

There are various types of flip-flops, but basically these change state on the edge of the control signal, and in some cases the data input(s). A classic D flip-flip is most like a latch, except it only looks at the input on a particular edge of the clock and freezes the output all the remaining time.

  • \$\begingroup\$ so is there is any difference between latch and flip flop or not ? \$\endgroup\$ Nov 7, 2011 at 7:00
  • \$\begingroup\$ @ankur.trapasiya: Yes. \$\endgroup\$ Nov 7, 2011 at 13:08
  • \$\begingroup\$ hmmm... cleared somewhat..!! what i understood is flip flop needs a clock and a latch doesn't need it. \$\endgroup\$ Nov 7, 2011 at 14:21
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    \$\begingroup\$ @ankur.trapasiya: yes, latches don't have a clock input but they have a corresponding input: most of the time called ENABLE. The clock input of a D-Flip-Flop is edge sensitive, the enable input of a latch is level sensistive, i.e. the output changes when enable is active and the input changes. \$\endgroup\$
    – Curd
    Jan 7, 2014 at 15:22
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    \$\begingroup\$ @Jbord: You are making this too complicated. Latches are level-gated, and flip-flops are edge-clocked. That's pretty much all that there is to it. \$\endgroup\$ Nov 17, 2016 at 21:40

A latch is an example of a bistable multivibrator, that is, a device with exactly two stable states.
These states are high-output and low-output.
A latch has a feedback path, so information can be retained by the device.
Therefore latches can be memory devices, and can store one bit of data for as long as the device is powered.
As the name suggests, latches are used to "latch onto" information and hold in place.
Latches are very similar to flip-flops, but are not synchronous devices, and do not operate on clock edges as flip-flops do.

enter image description here

A flip-flop is a device very like a latch in that it is a bistable mutivibrator, having two states and a feedback path that allows it to store a bit of information.
The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs can change as soon as the inputs do (or at least after a small propagation delay).
A flip-flop, on the other hand, is edge-triggered and only changes state when a control signal goes from high to low or low to high.
This distinction is relatively recent and is not formal, with many authorities still referring to flip-flops as latches and vice versa, but it is a helpful distinction to make for the sake of clarity.

enter image description here

  • \$\begingroup\$ A latch is not a (bistable or any other) multivibrator. \$\endgroup\$
    – Curd
    Jan 7, 2014 at 15:17

The difference between latches and flip-flops is, their outputs are constantly affected by their inputs as long as the enable signal is present. When they are enabled, their content changes immediately when their inputs change. Flip-flops have their content change only either at the rising or trailing edge of the enable signal. This enable signal controls the clock signal. After the rising or trailing edge of the clock, the flip-flop content remains constant even if the input changes.


The difference is in the intended use, mostly. A flip-flop is a general idea and has variations - how it is triggered, JK inputs or D, and all that. Flips can be used for counters, shift registers and all the other uses found in texts and online articles about flip-flops.

A latch is one particular use, where a set of flip flops (could be as few as one, I suppose) is given boolean levels, clocked, and thereafter hold those values constantly on their outputs. A snapshot, so to speak, of a binary value. No altering of the outputs values occur, except when new inputs are clocked in, or the latch is cleared which means setting all outputs to zero.

D-type flip flops are the obvious choice, but exactly what you use or how it is triggered isn't vital to the idea of what a latch is, even if important in the particular circuit or chip you're designing or using.


A transparent latch is a device with a data input and a control input. The control input has two states which may be called "track" and "hold". Some devices will regard a "high" on the control input as "track" and a low input as "hold"; others do the opposite. Whenever the control input is in the "track" state, the state of the output will continuously attempt to follow the state of the data input (there will a short delay between the time the data input changes and the output reflects the change). If the control input goes from the "track" state to the "hold" state, provided that the last change to the data input has had a chance to reach the output, the output will hold its value until such time as the control input goes back to the "track" state.

While transparent latches may be used in many ways, it's important to understand at least two usage scenarios. In one scenario, the latch is used to turn a signal that will sometimes hold valid data and sometimes hold invalid data, into a signal which will always hold valid data. This is done by keeping the latch in the "hold" state any time the data input might not match the desired output data. To change the latched data, one would put the desired data on the input, then set the latch briefly to "track" state and back to "hold" state, being careful that the data input does not change to an unwanted value while the "hold" signal is active. This arrangement could be used to e.g. control 64 outputs using eight control signals and eight data signals. Each control signal operates eight latches, one of which is wired to each of the eight data signals. One could use edge-triggered flip flops just as easily as latches, but the circuitry for a latch is somewhat simpler. Note that an edge-triggered flip flop in this scenario would ideally trigger on the transition from "hold" to "track".

In the second usage scenario, the input may not be meaningful at the time the latch switches to "transparent", but will become meaningful prior to the latch switching to "hold". If the devices that use its output won't care about its state until some time after the latch has switched to "hold", then it will be the state of the data input at that time which will be fed to the output. One may be able to use an edge-triggered flip flop in this scenario, but it must trigger on the transition from "track" to "hold". Note that if the data input to the latch becomes valid a significant time before the transition from "hold" to "track", the output will do likewise. By contrast, the output of a flip flop would only become valid when the clock changed.


the main difference is latch is level triggered for which race around condition arises in JK-latch and T-latch where as there is no race around condition in JK-FF and T-FF..and flipflops are edge triggered so no race around condition in FF.


The main difference between latches and flip-flops is that for latches, their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either at the rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising or falling edge of the clock, the flip-flop content remains constant even if the input changes

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    \$\begingroup\$ This doesn't seem to add anything not already covered in Prasanth's answer that was posted over two years ago. \$\endgroup\$
    – PeterJ
    May 7, 2014 at 3:16
  • \$\begingroup\$ @PeterJ: It does correct the grammar (original answer had an unresolved antecedent). Should have been an edit to the earlier answer, though. \$\endgroup\$
    – Ben Voigt
    Nov 17, 2016 at 21:04

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