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I'm trying to build an 8bit counter in Verilog. I specifically need to create a module that I instantiate 8 times. I have followed the diagram below (and assumed that I can just build on it to make it 8 instead of 4 bits). It appears what I have built instead is a shift register, it can shift ones and zeros - instead of 0001 -> 0011 I need 0001 -> 0010 (duh!). I feel as though I have misinterpreted the circuit diagram, as my logic seems otherwise sound. Any help much appreciated!

4 bit counter

TFlipFlop:

module tflfl(t, clk, clr, q);

input t;
input clk;
input clr;
output reg q;


always@(posedge clk, negedge clr)
    begin
        if(~clr)
            q <= 1'b0;
        else
            q <= t;
    end

endmodule

Modular Implementation:

tflfl t1(.t(enable), .clk(clock), .clr(reset), .q(q0));    
tflfl t2(.t(q0), .clk(clock), .clr(reset), .q(q1));
tflfl t3(.t(q1 && q0), .clk(clock), .clr(reset), .q(q2));
tflfl t4(.t(q2 && q1 && q0), .clk(clock), .clr(reset), .q(q3));
tflfl t5(.t(q3 && q2 && q1 && q0), .clk(clock), .clr(reset), .q(q4));
tflfl t6(.t(q4 && q3 && q2 && q1 && q0), .clk(clock), .clr(reset), .q(q5));
tflfl t7(.t(q5 && q4 && q3 && q2 && q1 && q0), .clk(clock), .clr(reset), .q(q6));
tflfl t8(.t(q6 && q5 && q4 && q3 && q2 && q1 && q0), .clk(clock), .clr(reset), .q(q7));
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  • \$\begingroup\$ I see your code is not strictly following the diagram. The T if t1 should be q0 & enable. And of the others it should be and of two inputs only, not incremental. And suddenly you will see a pattern, which will make it easy to define a generic N-bit counter using generate loops... \$\endgroup\$
    – Eugene Sh.
    Commented Feb 23, 2016 at 21:05
  • \$\begingroup\$ Your TFF is written with the functionality of a DFF. \$\endgroup\$
    – Greg
    Commented Feb 23, 2016 at 21:12
  • \$\begingroup\$ @eugenesh. Do you mean the T in t2? Thanks for the help! \$\endgroup\$
    – DAnsermino
    Commented Feb 24, 2016 at 17:36

3 Answers 3

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Your schematic shows a T-type flip-flop, which toggles when its input is high. Your rtl code, on the other hand, implements a regular D-type flip-flop. Your module should instead read:

always@(posedge clk, negedge clr)
begin
    if(~clr)
        q <= 1'b0;
    else
        q <= q ^ t;
end

By XOR'ing the output with the input, you will toggle the state when t is high, creating a T-type flip-flop.

The module instantiation is also different from the schematic. Your t inputs are all missing the && enable that the leftmost AND gate in the schematic implements.

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Is it an 8bit binary counter being built? Like 0000 0001 -> 0000 0010 -> 0000 0011 -> ?

Should it be specifically done only with T Flip Flops only?

May be a JK FF chain. Pull all the J&K high. Clock to the first FF. Connect the Q outputs directly to the clocks of consecutive FFs (If it's ~Clock input) Otherwise use ~Q output to clock.

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The diagram is shift 1: (reset) 000 -> 100 -> 110 -> 111 -> 111

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  • 1
    \$\begingroup\$ Look again: The "non-clock" input is not labelled D, but T. \$\endgroup\$
    – greybeard
    Commented Nov 7, 2023 at 16:39

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