# Port Connection Rules in Verilog

I am a beginner in Verilog

I would like to know why the port connection rules as outlined in the attached description are necessary.

Why must inputs be internally of a net type signal? And similarly, why outputs must be externally connected to a net type signal?

In Verilog, you can only do a constant assignment to a net type. A reg type is used in an always block to assign something based on a sensitivity list (it can be synchronous, e.g. flip-flop, or asynchronous, e.g. latch, or gate). A net type is used for assignments using the assign keyword or when connecting ports.
When you connect something to a port using the .portName(net) directive (or even the instanceName(net) method), it is a constant assignment, and hence requires the target to be a net.
• A reg type is used to store data (ish) - the value for the reg variable will be based on one or more inputs.
• A net type on the other hand is used to simply wire two things together - all parts of the net will forever be identical to the one and only input.