In Verilog, you can only do a constant assignment to a
net type. A
reg type is used in an
always block to assign something based on a sensitivity list (it can be synchronous, e.g. flip-flop, or asynchronous, e.g. latch, or gate). A
net type is used for assignments using the
assign keyword or when connecting ports.
When you connect something to a port using the
.portName(net) directive (or even the
instanceName(net) method), it is a constant assignment, and hence requires the target to be a
To think of it another way:
reg type is used to store data (ish) - the value for the
reg variable will be based on one or more inputs.
net type on the other hand is used to simply wire two things together - all parts of the net will forever be identical to the one and only input.