I know of a few ways to generate a sine wave; Op-amps, 555, LC, crystals, or microcontrollers. But none of those would really work for a frequency as high as 900 MHz. I have heard of phase lock loops, but I don't know how to use one. What's the highest factor I could multiply my reference frequency by and still have it end up with the expected output frequency, and how do I divide the frequency leaving the VCO? Is a VCO part of the PLL or are they separate components? Will my output be a sine wave if my reference frequency is a sine wave, or do these only output square waves?
One approach would be to use a simple single-chip transmitter designed for the 902-928 MHz ISM band. Here is a typical circuit:
This chip uses a PLL and internal divider to lock to a reference crystal. Power output is +23dBm (200mW) and it does not require a uC to set it up.
There are a number of app notes and a somewhat pricey eval board available from the supplier.
In answer to your question about a minimum comparison frequency for a PLL, there is no minimum, but the loop filter frequency and the lock-in time will increase proportionally to the inverse of the comparison frequency (all other things being equal), so if you compare at 100Hz vs. 10MHz it will take 100,000 times as long to lock in and stabilize.