# AVR external interrupt triggering by the falling edge: for how long should I keep signal low to guarantee triggering?

The question header appeared to bee too long. I'm sorry for that.

So I have a schematic generating a short LOW on INT0 pin of ATmega48PA. From the simulation I figured out that the LOW level will be there for about 800 ns. I plan to clock the AVR from internal RC with 1:8 divider which means 1 MHz Fosc.

How do I make sure that the interrupt will be triggered?

I make some reading of the datasheet but I was looking in a wrong chapters or there is no such information.

Could you please point me into the right direction to find needed info?

Thank you!

From the datasheet, for the description of ISC11, ISC10: