Estimating error due to Vref deviation on delta-sigma adc

Question

I am trying to estimate the error caused by deviation on the reference signal for the following 22 bit Delta-Sigma ADC and high precision linear voltage regulator:

http://ww1.microchip.com/downloads/en/DeviceDoc/20001950F.pdf http://www.linear.com/product/LTC6655

I've followed the design guide of National Semiconductor on "voltage reference selection basics" but although it is not mentioned anywhere I think the error estimation only applies for SAR ADCs (in my result, I have a typical error of 10.1 bits).

Hence my question, how do I estimate the error due to deviation in the reference signal of a Delta-Sigma ADC? I am measuring DC voltage (a battery).

Answer 1

The output of the ADC is with respect to the reference voltage. If your reference is 1% too low, then your output will be about 1% too high (1/0.99 ~ 1.01).