The following circuit is given:

The op amp circuit

I needed to calculate the effective value of the output voltage, for an input effective value of 1mV: $$ U_a=\frac{\frac{1}{jwC}}{R_1+\frac{1}{jwC}}*U=\frac{1}{1+jR_1wC}*U=\frac{1}{1+j*10.053}*1mV=\frac{1}{10.103*e^{j*84.32}}*1mV=0.099*e^{j*-84.32}*1mV\approx 98.9\mu V*e^{j*-84.32} $$ Therefore the amplitude of the output voltage is: $$ \hat{u}=\sqrt{2}*U_{eff}=\sqrt{2}*98.9\mu V\approx 139.866\mu V $$ I wanted to verify the result and used a circuit simulation tool (circuitlab). I received a surprising plot for the output voltage and current:

enter image description here enter image description here

As you can see, there is an interesting offset applied in some way. Can someone explain me why voltage/current look like that?

EDIT: Input current of both terminals:

enter image description here

  • 3
    \$\begingroup\$ If you want to include effects like input offset voltage and current, CircuitLab is probably not the best simulator to use. Get the vendor SPICE model for the specific op-amp you're interested in and then use the simulator tool that the model is designed to work with (for example LTSpice for LT products, Tina-TI for TI products, etc.) And still be careful that the model actually includes the effects you want to study. \$\endgroup\$
    – The Photon
    Feb 27 '16 at 19:15
  • 2
    \$\begingroup\$ If you're really implementing this circuit mind that 1Mohm resistor there. In simulation the signal might appear good, but in practice the thermal noise generated by the resistor can be a nightmare if you compare it to your 1mV signal. I'd strongly recommend you to low that resistance and decrease the capacitor value to maintain the same behaviour improving overal noise. \$\endgroup\$
    – PDuarte
    Feb 27 '16 at 19:18
  • 1
    \$\begingroup\$ @ThePhoton "And still be careful..." - one cannot stress this too much. Fun fact: When Mike Engelhardt (the guy who's email address is ltspice@linear.com) gives seminars about LTSpice, he demonstrates some broken OpAmp models (provided by their respective vendors, IIRC). He plots the output current and the current into the supply pins, and surprise: While the supply pins just draw their specified quiescent current, the output swings happily and provides something like +/- 50 mA ;-) KCL, anyone?! \$\endgroup\$
    – zebonaut
    Feb 27 '16 at 19:34
  • \$\begingroup\$ @PDuarte I'm sure you meant to say "increase the capacitor value" ;-) \$\endgroup\$
    – zebonaut
    Feb 27 '16 at 19:52
  • \$\begingroup\$ @zebonaut Sure! Tks for saying! \$\endgroup\$
    – PDuarte
    Feb 27 '16 at 19:53

You're feeding the OpAmp's non-inverting input via a fairly high-value resistor (1 MΩ). It seems like the simulation considers the TL081's input offset current with a value of 50 pA, because your (unity gain amp = buffer) produces an output offset voltage of 50 µV = 1 MΩ * 50 pA, ignoring the sign (simulation says - 50 µV).

To be sure, plot the current into the "+" pin of your TL081 and check if it's 50 pA.

The output offset current in your picture is actually anything that will "leak" into the "-" input (theoretically zero, practically equal to the input offset current of this very pin). Proof: Kirchhoff's current law - there is nothing else connected to the output, so anything coming from the output must be going the only possibly way which is the inverting input.

Fun fact: The value I expect you will see as the input offset current into the non-inverting input matches what you already see as the input offset current into your inverting input ;-)

As others have already mentioned, the TL081 has an input offset voltage some orders of magnitude higher than the error you see caused by the input offset current. As you are using your OpAmp as a buffer (gain = 1), your input offset error translates directly to your output offset error. In a practical circuit, this would be your main concern, and the lesson to be learned here is this: Simulations help you understand stuff, but they are always to be taken with a grain of salt. You are not done designing a circuit unless a simulation tells you exactly the same story as a breadboard on the bench, tested with instruments you trust. Any difference between the simulated and the real picture may be tolerated only if you have a good explanation. If the picture on the scope and the simulator's waveforms don't match, improve the simulation until they do and double, triple, ... check your practical circuit. But as you are asking this question, I guess you know already ;-)

Also, the effect that caught your attention is one of the reasons why circuit designers try to stay away from high-value resistors (say: above 100 kΩ) in signal-processing circuits if they can, because practical parasitic effects like leakage, offset etc. start to become annoying once you get into this range. If your circumstances permit, try to decrease the resistor's value and increase the capacitance just by the same factor; the RC time constant will remain the same and you gain the freedom to neglect parasitics. Also, low-value capacitors are tricky: Any parasitic capacitance (OpAmp input capacitance, layout traces, ...) are in parallel with C1 and increase the effective value to, say, 205...220 pF, which is a considerable error.

Edit (in response to comment):

The start-up behaviour (change of offset at the beginning of the plot) is just the DC offset current charging the 200 pF capacitor. For a DC analysis, we can consider your AC source to be a short and we end up with this scenario - a 50 pA current source connected to a parallel capacitor and resistor:

OpAmp Offset Simulation

The current source charges the capacitor, and because of the resistor, the voltage reaches a steady state after a while. Note that the RC time constant is 200 µs - as can be observed in both simulations, yours just has the additional AC component of your source V2.

  • \$\begingroup\$ Note that TL081 also has a 15 mV Vos spec, so the 50 uV offset resulting from the offset current here is likely to be swamped by the offset voltage effect in real life. \$\endgroup\$
    – The Photon
    Feb 27 '16 at 19:20
  • \$\begingroup\$ @ThePhoton Sure, this is a simulation (and not real life), and I'm happy to see that the model even considers some of the most basic parasitics. Also, many practical circuits don't care much about small offsets, but then again, what's "many circuits" and what's not ;-) \$\endgroup\$
    – zebonaut
    Feb 27 '16 at 19:29
  • \$\begingroup\$ Yes, the input currents of both terminals are 50pF, although they do not have equal phase (see EDIT in the question), according to simulation. Ok, so I understand that the offset is caused by the input offset voltage of the op amp, but what is causing the shift (change of offset) in the very beginning of the plot? Great answer btw, thanks! \$\endgroup\$
    – Daiz
    Feb 27 '16 at 21:15

It's hard to tell because the supply is not shown and the model of the opamp might have some limitations as well.

Real OpAmps always have some offset. What can be seen here is probably only some small systematic offset. For a real opamp the output is usually not zero for zero input, so you need a small voltage the drive the output to zero.

What happens if you connect the input to zero volts?

If you have a look at the datasheet you can see that the random offset is in the range of several mV, so the few uV is nothing to worry about.


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