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How can I find the Vm of a pseudo nmos inverter? Since I dont know the Vds of neither of my transistors I cant determine in which region they are.

http://imgur.com/4i37w3s

The circuit and some parameters are in that link. Wn = 9u is missing there tho.

EDIT1:

LTSpice Netlist

M1 N002 N003 0 0 T15DN l=0.6u w=9u
M2 N001 0 N002 N001 T15DP l=0.6u w=3u
V1 N001 0 5V
V2 N003 0 5V
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~2\LTC\LTSPIC~1\lib\cmp\standard.mos
.include T15D_models.txt
.dc V2 5 0 0.1
.backanno
.end

T15D_models.txt

.MODEL T15DN NMOS LEVEL=3 PHI=0.7 TOX=9.5E-09 XJ=0.2U TPG=1
+ VTO=0.7 DELTA=8.8E-01 LD=5E-08 KP=1.56E-04
+ UO=420 THETA=2.3E-01 RSH=2.0E+00 GAMMA=0.62
+ NSUB=1.40E+17 NFS=7.20E+11 VMAX=1.8E+05 ETA=2.125E-02
+ KAPPA=1E-01 CGDO=3.0E-10 CGSO=3.0E-10
+ CGBO=4.5E-10 CJ=5.50E-04 MJ=0.6 CJSW=3E-10
+ MJSW=0.35 PB=1.1
.MODEL T15DP PMOS LEVEL=3 PHI=0.7 TOX=9.5E-09 XJ=0.2U TPG=-1
+ VTO=-0.95 DELTA=2.5E-01 LD=7E-08 KP=4.8E-05
+ UO=130 THETA=2.0E-01 RSH=2.5E+00 GAMMA=0.52
+ NSUB=1.0E+17 NFS=6.50E+11 VMAX=3.0E+05 ETA=2.5E-02
+ KAPPA=8.0E+00 CGDO=3.5E-10 CGSO=3.5E-10
+ CGBO=4.5E-10 CJ=9.50E-04 MJ=0.5 CJSW=2E-10
+ MJSW=0.25 PB=1
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  • \$\begingroup\$ What is the definition of Vm? \$\endgroup\$
    – Mario
    Feb 28, 2016 at 17:25
  • \$\begingroup\$ @Mario Its threshold voltage. Vm=Vin=Vout \$\endgroup\$
    – omerfirmak
    Feb 28, 2016 at 17:39
  • \$\begingroup\$ Are you sure that it isn't Vin for Vout=VDD/2? \$\endgroup\$
    – Mario
    Feb 28, 2016 at 17:40
  • \$\begingroup\$ @Mario, the question explicitly asks for Vm and LTSpice sim shows that its 1.84V. Im not quite sure about that tho, i am no expert in Spice. \$\endgroup\$
    – omerfirmak
    Feb 28, 2016 at 17:43

1 Answer 1

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If we are looking for the voltage where Vin=Vout we can first assume (but we don't know it for sure) that MP is in the linear region. So we take the equation for the linear region (which I'm too lazy to type in) and set Vds to (5V-Vin) and Vgs to 5V.

Then we look at MN, since Vin=Vout it will be in saturation. Therefore we use the equation for saturation. We set Vgs to Vin.

Since the drain current for both transistors is the same, we can equate the two expressions and solve for Vin.

In a final step we check our assumption, that MP is indeed in linear region.

Update:

If you want your hand calculation to match with your simulation you have to use a simpler model.

.model PMOS pmos (KP= 48e-6 VT0=-0.95)
.model NMOS nmos (KP=156e-6 VT0=0.7)

enter image description here

The text in blue is my "hand calculation" and it agrees perfectly.

Please note that due to the condition Vin = Vout I am allowed to connect the output to the input.

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  • \$\begingroup\$ I did exactly that before posting this question. But that doesnt produce a result anywhere close to what LTSpice sim shows. Which is 1.84-1.83V. \$\endgroup\$
    – omerfirmak
    Feb 29, 2016 at 18:57
  • \$\begingroup\$ That's hard to believe. Please, post your LTSpice netlist. \$\endgroup\$
    – Mario
    Feb 29, 2016 at 19:02
  • \$\begingroup\$ I edited it in to the question. \$\endgroup\$
    – omerfirmak
    Feb 29, 2016 at 19:17
  • \$\begingroup\$ Jeez, I forgot to add Wn=9u to my Kn calc. Just left it at 130*Wn and ignored the Wn. I am the worst. Thank you for your time! \$\endgroup\$
    – omerfirmak
    Feb 29, 2016 at 20:16

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