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I am using DAC3484(dac) and xc7k160t-1ffg676(fpga) in my design. DAC is interfaced to FPGA. DAC data rate is 153.6MHZ. DAC data lines should be length matched within some tolerance. How to decide that tolerance value??

I have seen in many sites they say that tolerance is decided based on setup and hold time requirements at receiver. Can someone please clearly explain how to calculate the tolerance with the above said dac data rate and setup and hold time of the dac3484 chip??

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How to calculate it.

The DAC expects data with a timing reference with respect to the clock. The data may change before the setup time has expired, but must remain valid afterwards. The data may change after the hold time has elapsed, but must stay valid before. This gives you a 'valid' window, and a 'may change' window.

As a first step, arrange the FPGA to change the data in the middle of the 'may change' window with respect to the clock. Make sure the FPGA uses the correct clock edge. Some FPGAs contain I/O timing modification registers, and clock retiming servos to help (or complicate) this.

Now you've done this, see what effect the FPGA propagation skew has on your timing window, it will have eaten into your timing budget a little.

Now you can see what your setup and hold times are at the start of the interconnect. This will give you an error budget for the tracking skew. Now you can tolerance the lengths of the lines. Remember the speed of light is about one foot/nS in air, about 70% of that on PCB.

Wiggling the lines is the last thing a layout designer should be doing. The first thing is making sure there is an intact ground plane route from the FPGA to the DAC that runs parallel with the clock and data lines to assure data integrity. The zeroth thing is making sure that currents induced by the data transitions do not create voltages across the DAC references or analogue outputs. Most DACs have pinnouts that are pre-thought-out to make this possible.

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  • \$\begingroup\$ Thanks for the quick reply. I want it in terms of numbers. Assuming data is launched at rising edge and captured at falling edge. basically databus is stable (centered) at the capturing edge of receiver(dac). Just for example Time period= 6.5ns. setup time(data to be valid before the capturing edge of clk)= 2ns. hold time(data to be valid after the capturing edge of clk)= 1.5ns. Now what will be the tolerance in this case?? \$\endgroup\$
    – suma
    Feb 29, 2016 at 8:28
  • \$\begingroup\$ Of course you want it in numbers! That's what you have to do, as the design engineer. Draw a diagram. It looks like you have a 3nS 'may change' window based on the DAC input specs. Don't forget to add in the tolerance of the FPGA output skew. With a rising here, falling there specification, don't forget to add in the clock duty cycle deviation from 50%, which will eat into both the setup and hold margins. We tend not to use rising/falling for higher speeds for that reason! I would expect the board Er homogenaity skew to be minimal. \$\endgroup\$
    – Neil_UK
    Feb 29, 2016 at 9:03
  • \$\begingroup\$ As a side note (but definitely on topic), keep in mind that FPGAs can have huge timing skews as the bond wires can be measured in inches; some tools take this into account when generating a timing report, but some do not. You will need to find out if the tool your FPGA person is using generates a true pin timing report. \$\endgroup\$ Feb 29, 2016 at 9:30
  • \$\begingroup\$ If we use rising/rising then skew can be 4.5ns(T-tsu)max. In case of rising/falling skew can be 1.25ns(T/2 - tsu) max. Assuming everything else is ideal (like duty cycle exact 50%). Plz correct me if i am wrong. \$\endgroup\$
    – suma
    Feb 29, 2016 at 9:31
  • \$\begingroup\$ TI has done a great deal to make this part relatively easy to put down on a PCB - look at pages 15 and 16 of the DAC datasheet and you will see that the setup and hold times are quite configurable. \$\endgroup\$ Feb 29, 2016 at 9:49

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