I would like to have an FPGA chip that is tightly connected to an image sensor. Ideally I would like to read all image columns (or rows) in parallel straight into the FPGA. Does such hardware exist?


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  • \$\begingroup\$ Do you any other requirements ? Like price range or desired performance ? \$\endgroup\$ – MaximGi Feb 29 '16 at 9:07
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    \$\begingroup\$ There are many of them, but not a FPGA and sensor in the same chip. Possible like: opalkelly.com \$\endgroup\$ – Marko Buršič Feb 29 '16 at 9:07
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    \$\begingroup\$ no, you might find a dev board/kit that does something like this though. Not only will you not find an FPGA with a built in camera (I assume that's what you mean by image sensor) but you'll also need to look carefully at how much memory the FPGA has. Depending on your algorithm you might need a frame store and many FPGAs have fairly limited built in memory \$\endgroup\$ – Will Feb 29 '16 at 9:08
  • \$\begingroup\$ Check out the Apertus.org 'Axiom Beta', an open-source cinema camera based on the Xilinx Zynq 7020-based FPGA (Digilent MicroZed) and a Cmosis 4K image sensor. The sensor has 64 LVDS pair outputs, 32 of which have been routed into the FPGA, & at 600mbps each pair they're getting hundreds of frames per second. Not quite what you were wanting, but... \$\endgroup\$ – Techydude Feb 29 '16 at 9:52

The Fraunhofer Institute for Integrated Circuits IIS (Design Automation Division EAS) researches "Vision System on Chip" (VSoC) devices.

The current devices is a 1 MegaPixel CCD image sensor with

  • analog pre-processing in the columns
  • configurable ADC
  • post-processing in a FPGA and
  • high-level processing in an ARM dual-core CPU (Xilinx Zynq-7000 platform).

sensor http://www.mikroelektronik.fraunhofer.de/fileadmin/_processed_/csm_NL_60_13_01_IIS_EAS_Vision-Sensor_f%C3%BCr_das_Kameramodul_final_61286ac0c9.jpg

It's a research platform.


  • \$\begingroup\$ The transform imagers by Prof. Ryan Robucci would also be a good place to start. The pre-processing is done in analog and then output is sent to a FPGA. A DCT, etc, is basically free in analog. \$\endgroup\$ – b degnan Feb 29 '16 at 13:52

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